Synopsys ARC Embedded Vision Processors Deliver 35 TOPS

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eetimes.com, Sept. 16, 2019 – 

Synopsys has launched its latest generation of embedded vision processors with deep neural network (DNN) accelerator delivering what it claims is an industry-leading 35 TOPS (tera operations per second) performance for artificial intelligence (AI) intensive edge applications. Also introduced is a functional safety processor version for automotive advanced driver assist systems (ADAS), radar/lidar, and automotive sensor system on chip (SoC) development.

Based on the ARCv2 RISC instruction set architecture, the new DesignWare ARC EV7x vision processors feature a 1, 2 or 4-core heterogeneous architecture which integrates vector DSP, vector FPU, and neural network accelerator to enable a variety of intelligent automotive and consumer applications with integrated AES encryption. The optional DNN accelerator scales from 880 to 14,080 MACs to enable a system that delivers up to 35 TOPS performance in 16-nanometer (nm) FinFET process technologies under typical conditions, four times the performance of the previous generation ARC EV6x processors.

In a telephone briefing with EE Times, Gordon Cooper, product marketing manager for Synopsys EV processors, said the EV7x processors are an optimization of the EV6x processors, but it was not just about adding four times the MACs. He said adding MACs was the easy part of scaling CNN (convolutional neural network) graph performance, but what's really critical is improving memory bandwidth required for external memory accesses in order to minimize power consumption. This bandwidth handling in the new processors means it is possible to scale to 100 TOPS, allowing use of lower cost DRAM interfaces.

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