Greetings from SiFive!
   
The momentum surrounding the RISC-V Instruction Set Architecture (ISA) is growing on a global scale. SiFive, the company founded by the inventors of the RISC-V architecture, has been actively promoting RISC-V based cores and custom silicon solutions throughout the world via technical symposiums that aim to enlighten and engage semiconductor and system designers. We are hosting six symposiums in Europe in May, and we cordially invite you to attend the one closest to you. These events are highly educational and present many opportunities for engagement within the hardware community. Each event will feature presentations by industry veterans, ecosystem partners and academic luminaries. Attendees will learn about the RISC-V ecosystem, and the SaaS-based approach that is enabling fast access to the custom cores, design platforms, and custom SoC solutions for emerging applications.
     
WHEN & WHERE:
 
May 13, 2019, Cambridge - View Agenda & Register
 
May 15, 2019, Grenoble - View Agenda & Register
 
May 17, 2019, Stockholm - View Agenda & Register
 
May 20, 2019, Moscow - View Agenda & Register
 
May 23, 2019, Munich - View Agenda & Register
 
May 29, 2019, Amsterdam - View Agenda & Register
 
We look forward to meeting you!
  
Sincerely,
The SiFive Team  
  
SiFive, Inc., 1875 South Grant Street, Suite 600, San Mateo, CA 94402
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