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Hot Product
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71 "Hot Product" Solutions

1
MIPI D-PHY Tx 4 Lanes - TSMC7FF18, North/South Poly Orientation
Synopsys offers a high-quality, silicon-proven D-PHY IP solutions that are available today in advanced process technologies.

2
SAS Initiator Controller IP
This Initiator Controller IP supports 12.0/6.0/3.0/1.5Gbps data rates and many enterprise level features including SCSI SBC-2 End-to-End Protection (DIF) and high performance, full duplex DMA with IEEE 1212.1 Scatter/Gather.

3
AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM
  • 1. TSMC Soft IP qualification (IP9000)

4
Cadence_test_hot_product
test

5
DDR5 Controller and PHY

Cadence has prototyped the world's first IP interface in silicon for a preliminary version of DDR5 standard. A test chip contains the next-generation memory interface IP based on the industry c...


6
Design IP Portfolio
Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.

7
DesignWare Controller IP for CCIX 1.0 and PCIe 4.0
Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance cloud computing applications.

8
DesignWare Controller IP for CCIX v1.0

Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance clo...


9
DesignWare DDR4/3 PHY IP in TSMC 12FFC Process

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DD...


10
DesignWare HDMI 2.1 RX IP for TSMC 12FFC Process

The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement ...


11
DesignWare IP for PCI Express 4.0 in Samsung 14LPP Process

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


12
DesignWare MIPI D-PHY IP for TSMC 7FF

The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanc...


13
DesignWare MTP ULP NVM IP for TSMC 180-nm

The Synopsys DesignWare® Multi-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increasing the write cycle endurance specification. The NV...


14
DesignWare Multi-Protocol 16G PHY IP in TSMC 12FFC Process
The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications.

15
DesignWare Multi-Protocol 25G PHY IP for TSMC 12FFC

The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


16
DesignWare PHY IP for PCI Express 4.0 in TSMC 16FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


17
DesignWare PHY IP for PCI Express in TSMC 12FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


18
Gen4SWITCH Multi-DS
PLDA s Gen4SWITCH Multi-DS Platform is the Industry s first PCIe 4.0 switch platform with multiple-downstream ports (up to 3 Downstream ports) using PLDA's XpressSWITCH IP.

19
I3C HCI Master Controller
The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility.

20
LPDDR4X multiPHY - TSMC12FFC18
The Synopsys DesignWare LPDDR4 multiPHY is a complete physical interface solution for many different kinds of JEDEC -standard mobile and PC/consumer SDRAMs.

21
PCI Express 4.0 PHY in TSMC 12FFC Process

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


22
SAS Target Controller IP for SSD and other Target applications
Primarily aimed at enterprise SSD Controller ASICs and FPGAs, but is also suitable for other SAS Target applications such as Tape Drive. Supports 12.0/6.0/3.0/1.5Gbps data rates and many enterprise level features including SCSI SBC-2 End-to-End Protection (DIF) and high performance, full duplex DMA with IEEE 1212.1 Scatter/Gather.

23
SATA 3.0 AHCI Host Controller
With similarly advanced processor off-load features and a flexible Phy Control Layer for interfacing with leading 6Gbps PHY/SERDES IP (e.g. Snowbush), it is an excellent choice for both Enterprise applications and consumer media server / STB applications.

24
SATA Controller for SSD and other Device products
CEVA SATA Device Controller is a mature, robust, RTL-based IP package which is already widely licensed to leading semiconductor vendors.Supporting the latest SATA3.0 specification for 6Gbps operation, it is especially suitable for high performance Solid State Drives (SSD).

25
SESAME uHD-BTF - 6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).

26
SMIC40LL DDR34/LPDDR23 PHY
B40LLDDRPHY-D34LP23 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combination of DDR speed and low power o...

27
SpRAM RHEA HD RR
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 320 k

28
SpRAM RHEA HD RR TSMC 180nm BCDGen2
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k

29
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M

sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M


  • REDUCE DIE COST
    • 35% d...

30
TSMC 180 RFID
Dolphin Integration contributes to enabling low-power Systems-on-Chip for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at...

31
UFS 3.0 Host Controller

The DesignWare® Universal Flash Storage (UFS) Host Controller IP is a standard-based serial interface engine for implementing the JEDEC UFS interface in compliance with the JEDEC UFS, UFS Host ...


32
UHS-II PHY Core IP

The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access t...


33
USB 3.1 PHY (10G/5G) - SS 10LPP x1 OTG, North/South Poly Orientation
This USB 3.1 PHY IP provides designers with the industry s best combination of low area and low power with support for the leading process technologies such as 14/16-nm FinFET.

34
XpressCCIX Controller IP for PCIe with Support for CCIX ESM
XpressCCIX is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation, and supporting the Cache Coherent Interconnect for Accelerators (CCIX) Extended Speed Mode (ESM) data rate.

35
XpressRICH3 - Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
PLDA PCIe 3.0 XpressRICH3 is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root port, switch, bridge and advanced features such as SR...

36
XpressRICH5 Controller Soft IP for PCIe 5.0

XpressRICH5 is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5 IP is compliant with the PCI Express 5.0 rev.0.7, 4.0, 3.1, 2.1, and 1....


37
GZIP-RD-A10
CAST provides practical, affordable intellectual property (IP) products and services for the electronic product development process, with a focus on popular 8- and 16-bit microprocessors, microcontrol...

38
Multiprotocol PMA
Silicon Creations has a range of Serializer-Deserializer IP built upon proven ring PLLs and high-speed line drivers and receivers. The PMA architecture is in production in over 25 SerDes, from 180n to...

39
Serializer - Deserializer IP
Silicon Creations has a range of Serializer-Deserializer IP built upon proven ring PLLs and high-speed line drivers and receivers. The PMA architecture is in production in over 20 SerDes, from 180n to...

40
ZipAccel-C - GZIP/ZLIB/Deflate Data Compression Core
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.

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