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Hot Product
  (84)
84 "Hot Product" Solutions

1
MIPI D-PHY Tx 4 Lanes - TSMC7FF18, North/South Poly Orientation
Synopsys offers a high-quality, silicon-proven D-PHY IP solutions that are available today in advanced process technologies.

2
SAS Initiator Controller IP
This Initiator Controller IP supports 12.0/6.0/3.0/1.5Gbps data rates and many enterprise level features including SCSI SBC-2 End-to-End Protection (DIF) and high performance, full duplex DMA with IEEE 1212.1 Scatter/Gather.

3
AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM
  • 1. TSMC Soft IP qualification (IP9000)

4
DDR5 Controller and PHY

Cadence has prototyped the world's first IP interface in silicon for a preliminary version of DDR5 standard. A test chip contains the next-generation memory interface IP based on the industry c...


5
Design IP Portfolio
Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.

6
DesignWare 56G Ethernet PHY IP
The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications.

7
DesignWare 56G Ethernet PHY IP in 7-nm

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurem...


8
DesignWare Controller IP for CCIX 1.0 and PCIe 4.0
Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance cloud computing applications.

9
DesignWare Controller IP for CCIX v1.0

Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance clo...


10
DesignWare DDR4/3 PHY IP in TSMC 12FFC Process

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DD...


11
DesignWare HDMI 2.1 Audio PLL IP in TSMC 12FFC
The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based applications.

12
DesignWare HDMI 2.1 RX IP for TSMC 12FFC Process

The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement ...


13
DesignWare IP for PCI Express 4.0 in Samsung 14LPP Process

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


14
DesignWare MIPI D-PHY IP for TSMC 16FFC
The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanced ...

15
DesignWare MIPI D-PHY IP for TSMC 7FF

The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanc...


16
DesignWare MTP ULP NVM IP for TSMC 180-nm

The Synopsys DesignWare® Multi-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increasing the write cycle endurance specification. The NV...


17
DesignWare Multi-Protocol 16G PHY IP in TSMC 12FFC Process
The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications.

18
DesignWare Multi-Protocol 16G PHY IP in TSMC 16FFPGL Process
The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications.

19
DesignWare Multi-Protocol 25G PHY IP for TSMC 12FFC

The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


20
DesignWare PHY IP for PCI Express 4.0 in TSMC 16FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


21
DesignWare PHY IP for PCI Express in TSMC 12FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


22
DesignWare SD/eMMC PHY IP in TSMC 12FFC
The DesignWare® SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines.

23
DesignWare UFS 3.0 Host Controller IP with Inline Encryption

The DesignWare® Universal Flash Storage (UFS) Host Controller IP is a standard-based serial interface engine for implementing the JEDEC UFS interface in compliance with the JEDEC UFS, UFS Host ...


24
Gen4SWITCH Multi-DS
PLDA s Gen4SWITCH Multi-DS Platform is the Industry s first PCIe 4.0 switch platform with multiple-downstream ports (up to 3 Downstream ports) using PLDA's XpressSWITCH IP.

25
High speed SAR-based analog-to-digital converter
The ADC is a high speed SAR-based analog-to-digital converter specified to operate from a nominal 1.2V analog supply and 1.2V digital supply in differential mode application and an additional 3.3V analog supply in single ended mode application.

26
I3C HCI Master Controller
The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility.

27
LPDDR4X multiPHY - TSMC12FFC18
The Synopsys DesignWare LPDDR4 multiPHY is a complete physical interface solution for many different kinds of JEDEC -standard mobile and PC/consumer SDRAMs.

28
ONFI 4.1 NAND Flash Controller
The Arasan NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.

29
PCI Express 4.0 PHY in TSMC 12FFC Process

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


30
SAS Target Controller IP for SSD and other Target applications
Primarily aimed at enterprise SSD Controller ASICs and FPGAs, but is also suitable for other SAS Target applications such as Tape Drive. Supports 12.0/6.0/3.0/1.5Gbps data rates and many enterprise level features including SCSI SBC-2 End-to-End Protection (DIF) and high performance, full duplex DMA with IEEE 1212.1 Scatter/Gather.

31
SATA 3.0 AHCI Host Controller
With similarly advanced processor off-load features and a flexible Phy Control Layer for interfacing with leading 6Gbps PHY/SERDES IP (e.g. Snowbush), it is an excellent choice for both Enterprise applications and consumer media server / STB applications.

32
SATA Controller for SSD and other Device products
CEVA SATA Device Controller is a mature, robust, RTL-based IP package which is already widely licensed to leading semiconductor vendors.Supporting the latest SATA3.0 specification for 6Gbps operation, it is especially suitable for high performance Solid State Drives (SSD).

33
SESAME uHD-BTF - 6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).

34
SMIC40LL DDR34/LPDDR23 PHY
B40LLDDRPHY-D34LP23 IP is compliant to JESD79-3F(DDR3), JESD79-4A(DDR4), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combination of DDR speed and low power o...

35
SpRAM RHEA HD RR
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 320 k

36
SpRAM RHEA HD RR TSMC 180nm BCDGen2
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k

37
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M

sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M


  • REDUCE DIE COST
    • 35% d...

38
TSMC 180 RFID
Dolphin Integration contributes to enabling low-power Systems-on-Chip for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at...

39
UFS 3.0 Host Controller

The DesignWare® Universal Flash Storage (UFS) Host Controller IP is a standard-based serial interface engine for implementing the JEDEC UFS interface in compliance with the JEDEC UFS, UFS Host ...


40
UHS-II PHY Core IP

The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access t...


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