53 "Cryptography" Solutions

CLP-630: Multi-Packet Manager Security Engine
The Multi-Packet Manager is a highly programmable and unique Security Protocol Accelerator specifically designed to efficiently process data for high capacity wireless and network applications. The en...

DesignWare ARC SEM Security Processors
The DesignWare® ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, hardware and physical attacks.

DesignWare Cryptography Software Library
DesignWare Cryptography Software Library includes a suite of widely used encryption and certificate processing functions required for embedded applications

Ellipsys-SB: Secure Boot
Ellipsys-SB is part of the Ellipsys Trust Framework which is Elliptic s solution to help device manufactures and system providers protect their product from tampering, cloning, and other threats. The...

EnSilica provide a comprehensive range of encryption and authentication IP for ASIC and FPGA targets with low resource usage and high throughput.

Multipurpose Security Protocol Accelerator
The configurable DesignWare® Multipurpose Security Protocol Accelerator (SPAcc) addresses complex security requirements for multi-function, highperformance SoC designs.

SPP-330: IPsec/TLS Multi-Protocol PDU Processor
The SPP-330 IPsec/TLS Multi-protocol PDU Processor is a member of Elliptic s highly-integrated Security Protocol Processors (SPP) family targeted at ASIC manufacturers and FPGA designers and supports ...

BA452 secure connection IP core
The BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations.

Chacha20-Poly1305 HP
Chacha20-Poly1305 high performance IP core for authenticated encryption.

CryptoManager Root of TrustCryptoManager Root of Trust - CryptoManager RISC-V Root of Trust Programmable Secure Processing Core
The CryptoManager Root of Trust is a fully-programmable hardware security core that protects against a wide range of attacks with state-of-the-art anti-tamper and security techniques to offer vendors security by design.

Ensigma Security (IPSec) Protocol Processing Engine
The high performance engine can process multiple gigabits of traffic with short IP packets (40 byte). Ensigma IPSec provides DMA type of interface for programming pointers to the security association data, packet pointers.

Ensigma Unified Security Engine (UNISec)
The Ensigma Unified Security Processor (USecP) combines the IPSec, MACSec and DTLS engines into a single unified multi-protocol processing engine supporting eight 1Gbps ports or one 10Gbps port.

eSecure : Single module for multiple security challenges
The eSecure IP is a complete standalone module that enables security applications by shielding the secret information from the non-secure application running on the main processor.

Inside Secure Root-of-Trust
Designed to be integrated in power constrained microcontroller or complex SoC, Inside Secure Root-of-Trust Engine is the vault that guards the chip most sensitive assets and that establishes the platform security foundations.

Programmable Root-of-Trust Engine
Inside Secure Programmable Root-of-Trust features a RISC-V 32-bit CPU and is delivered with its application development framework.

SHA-3 hashing function
The BA418 is crypto engine IP core for SHA-3 hashing functions compliant to NISTS s FIPS 180-4 and FIPS 202 standards.

Silex Insight BA451 MACsec Engine
The BA451 is a very scalable engine implementing the MACsec standard for high throughput applications.

Our proven Whitebox technology dissolves cryptographic keys into code. This hides it from anyone spying on the code or its execution. This is coupled with countermeasures (both cryptographic and obfuscation based) to defend against attacks on the Whitebox.

AES Encryption & Decryption with Fixed Block Cipher Mode AES-C
The AES-C IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key. An included configurable wrapper surrounds the AES-C core and implements its fixed Block Cipher mode of operation.

AES Encryption & Decryption with Programmable Block Cipher Mode AES-P
The AES-P IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

AES encryptor / AES decryptor - Symmetric Security Range
The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint.

Anti-Tamper technologies
Attacks against digital circuits can be performed by actively disrupting the device or by directly tampering with the device’s internal structure. These powerful attacks regroup attempts to inje...

Authenticated Encryption & Decryption AES-GCM128
The AES-GCM128 IP Core implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommendation for GCM and GMAC and the FIPS-197 Advanced Encryption Standard. The core can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

Cryptographic library for Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Digital Signature Algorithm (ECDSA)
The Software ECC is a cryptographic library providing the main ECDSA and ECDH functionalities

DES Cryptoprocessor
This core is a fully compliant implementation of the DES encryption algorithm. Both encryption and decryption are supported. ECB, CBC and triple DES versions are available. Simple, fully synchronous d...

The Dragon-QT combines Athena s TeraFire F5200 security microprocessor with Intrinisic-ID s Quiddikey-Flex secure key management. Intrinsic-ID s patented physically unclonable function (PUF) technolog...

High-quality random generation
Random number generation is a keystone in security. Secure-IC offers both True Random Number Generator (TRNG) resilient to harmonic injection for statistically independent sets of bits generation and ...

HMAC-SHA1 Authentication & Hashing function
IPX-HMAC-SHA-1 IP-Core is the hashing function required for the content integrity check and content identification as specified in DCI document v1.2. It is designed for Xilinx and Altera devices.

NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key.

Quiddicard is a key management and anti-counterfeiting software for remotely programming keys into ICs with Intrinsic-ID s Quiddikey-Flex secure key storage module. The PUF used by Quiddikey-Flex is a...

RSA Public Key Cryptography Exponentiation Accelerator
The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem.

Secure 128-bit Advanced Encryption Standard (AES) coprocessor
The Secure AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture (SPA, DPA[1] and fault hardened).

SHA-1 Secure Hash Function
TheSHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.

SHA-256 Secure Hash Function
The SHA256 IP core is a high performance implementation of the SHA-256 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-2. The core is composed of two main units, the SHA256 Engine and the Padding Unit as shown in the block diagram. The SHA256 Engine applies the SHA256 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.

Strong secret storage
Storing a secret in an electronic device implies leaving physical marks of the data stored, and thus is prone to direct reading or reverse-engineering. To avoid those traces, Secure-IC Strong Secret S...

Tunable Cryptography
Secure-IC offers a broad range of Cryptography technologies to cover customers’ needs, from Symmetric Cryptography to Asymmetric Cryptography and Hash functions.

They are designed to strike t...

XTS mode AES Processor
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encryption applications at sector (data unit) addressable level.

AES Encryption, 128-bit block cipher, which supports a choice of three key sizes (128,192 and 256-bits)
AES Encryption, 128-bit block cipher, which supports a choice of three key sizes (128,192 and 256-bits)

EC Ultra Elliptic Curve Cryptography Microprocessor
TeraFire EC Ultra IP cores accelerate EC point multiplies and ECDSA signs and verifies over NIST P-curves. Configurations can include as many P-curves as needed or can eliminate unnecessary curves to save system resources.

F5200 Embedded Cryptography Microprocessor
An embedded cryptography microprocessor core, a fast, efficient microprocessor designed for public key and secret key cryptography applications. With an area footprint starting at 25K gates and nearly 300 RSA-1024 private key operations per second, the F5200 provides more than 10X greater performance than competitive solutions with similar area.

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