43 "Cryptography" Solutions

CLP-630: Multi-Packet Manager Security Engine
The Multi-Packet Manager is a highly programmable and unique Security Protocol Accelerator specifically designed to efficiently process data for high capacity wireless and network applications. The en...

DesignWare ARC SEM Security Processors
The DesignWare® ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, hardware and physical attacks.

DesignWare Cryptography Software Library
DesignWare Cryptography Software Library includes a suite of widely used encryption and certificate processing functions required for embedded applications

Ellipsys-SB: Secure Boot
Ellipsys-SB is part of the Ellipsys Trust Framework which is Elliptic s solution to help device manufactures and system providers protect their product from tampering, cloning, and other threats. The...

SPP-330: IPsec/TLS Multi-Protocol PDU Processor
The SPP-330 IPsec/TLS Multi-protocol PDU Processor is a member of Elliptic s highly-integrated Security Protocol Processors (SPP) family targeted at ASIC manufacturers and FPGA designers and supports ...

BA452 secure connection IP core
The BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations.

CryptoManager Root of TrustCryptoManager Root of Trust - CryptoManager RISC-V Root of Trust Programmable Secure Processing Core
The CryptoManager Root of Trust is a fully-programmable hardware security core that protects against a wide range of attacks with state-of-the-art anti-tamper and security techniques to offer vendors security by design.

Ensigma Security (IPSec) Protocol Processing Engine
The high performance engine can process multiple gigabits of traffic with short IP packets (40 byte). Ensigma IPSec provides DMA type of interface for programming pointers to the security association data, packet pointers.

Ensigma Unified Security Engine (UNISec)
The Ensigma Unified Security Processor (USecP) combines the IPSec, MACSec and DTLS engines into a single unified multi-protocol processing engine supporting eight 1Gbps ports or one 10Gbps port.

eSecure : Single module for multiple security challenges
The eSecure IP is a complete standalone module that enables security applications by shielding the secret information from the non-secure application running on the main processor.

Programmable Root-of-Trust Engine
Inside Secure Programmable Root-of-Trust features a RISC-V 32-bit CPU and is delivered with its application development framework.

SHA-3 hashing function
The BA418 is crypto engine IP core for SHA-3 hashing functions compliant to NISTS s FIPS 180-4 and FIPS 202 standards.

Silex Insight BA451 MACsec Engine
The BA451 is a very scalable engine implementing the MACsec standard for high throughput applications.

Advanced Encryption Standard (AES) IP core 128/192/256
The AES provides AES-128, AES-192, and AES-256 encryption and decryption, as per FIPS-197, with a shockingly small resource usage, while allowing a large operating frequency.

AES Encryption & Decryption with Fixed Block Cipher Mode AES-C
The AES-C IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key. An included configurable wrapper surrounds the AES-C core and implements its fixed Block Cipher mode of operation.

AES Encryption & Decryption with Programmable Block Cipher Mode AES-P
The AES-P IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

AES encryptor / AES decryptor - Symmetric Security Range
The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint.

Authenticated Encryption & Decryption AES-GCM128
The AES-GCM128 IP Core implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommendation for GCM and GMAC and the FIPS-197 Advanced Encryption Standard. The core can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

Cryptographic library for Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Digital Signature Algorithm (ECDSA)
The Software ECC is a cryptographic library providing the main ECDSA and ECDH functionalities

The Dragon-QT combines Athena s TeraFire F5200 security microprocessor with Intrinisic-ID s Quiddikey-Flex secure key management. Intrinsic-ID s patented physically unclonable function (PUF) technolog...

HMAC-SHA1 Authentication & Hashing function
IPX-HMAC-SHA-1 IP-Core is the hashing function required for the content integrity check and content identification as specified in DCI document v1.2. It is designed for Xilinx and Altera devices.

Quiddicard is a key management and anti-counterfeiting software for remotely programming keys into ICs with Intrinsic-ID s Quiddikey-Flex secure key storage module. The PUF used by Quiddikey-Flex is a...

RSA Public Key Cryptography Exponentiation Accelerator
The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem.

Secure 128-bit Advanced Encryption Standard (AES) coprocessor
The Secure AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture (SPA, DPA[1] and fault hardened).

SHA-1 IP Core fully verified with NIST test vectors
SHA-1 IP Core fully verified with NIST test vectors, with a minimum latency: 84 cycles per block of 512 bits.

SHA-1 Secure Hash Function
TheSHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.

SHA-256 Secure Hash Function
The SHA256 IP core is a high performance implementation of the SHA-256 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-2. The core is composed of two main units, the SHA256 Engine and the Padding Unit as shown in the block diagram. The SHA256 Engine applies the SHA256 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.

AES Encryption, 128-bit block cipher, which supports a choice of three key sizes (128,192 and 256-bits)
AES Encryption, 128-bit block cipher, which supports a choice of three key sizes (128,192 and 256-bits)

DES Cryptoprocessor
This core is a fully compliant implementation of the DES encryption algorithm. Both encryption and decryption are supported. ECB, CBC and triple DES versions are available. Simple, fully synchronous d...

EC Ultra Elliptic Curve Cryptography Microprocessor
TeraFire EC Ultra IP cores accelerate EC point multiplies and ECDSA signs and verifies over NIST P-curves. Configurations can include as many P-curves as needed or can eliminate unnecessary curves to save system resources.

F5200 Embedded Cryptography Microprocessor
An embedded cryptography microprocessor core, a fast, efficient microprocessor designed for public key and secret key cryptography applications. With an area footprint starting at 25K gates and nearly 300 RSA-1024 private key operations per second, the F5200 provides more than 10X greater performance than competitive solutions with similar area.

NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key.

TeraFire 5200 Series 32-bit Cryptography Microprocessor
From the market leader in high performance public key cryptography cores comes the 5200 series, a fast and efficient public key cryptography solution with multiple size and performance options that can be matched to the requirements of your application.

TeraFire 6400 Series 64-bit Cryptography Microprocessor
The TeraFire 6400 series delivers over five times faster processing of RSA-2048 operations than the 5200 series architecture, while maintaining 100% code compatibility and 100% functional compatibility across the entire TeraFire® cryptography microprocessor family.

XTS mode AES Processor
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encryption applications at sector (data unit) addressable level.

Advanced Encryption Standard (AES) Engine
Advanced Encryption Standard (AES) engine is a highly configurable and multipurpose encryption/decryption engine. The AES engine can be used for wide range of requirements from low gate count to high performance.

AES Core
The es4001 AES core implements the Advanced Encryption Standard (Rijndael Algorithm FIPS 197) encoder and decoder.

ARC4 core
ES1020 core fully implements the ARC4 stream ciphering algorithm in hardware.

Cryptographic Software Library
Field-proven, high performance cryptographic software library for embedded applications Discretix cryptographic library offers an optimized software-only implementation of a variety of cryptographic...

DES Core - Low-gate count Data Encryption Standard
ES1040 core implements Data Encryption Standard (DES) cipher algorithms in hardware.

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