Implements a CAN 2.0 bus controller and provides an application layer that conforms to the ARINC 825 Avionics bus specification.

Implements a CAN protocol bus controller that performs serial communication according to CAN 2.0, and CAN FD specifications.

It is a complete reference design for a CAN node subsystem based on the CAN-CTRL CAN 2.0 & CAN FD Bus Controller IP Core. It can be used for evaluating the CAN-CTRL core, and it enables the rapid development of CAN FD applications or device prototypes.

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications.

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more cryptographically separated execution contexts for a high degree of security during code execution and for data storage and transfer to and from the processor.

The IEEE802_1AS is a complete IEEE 802.1AS hardware stack that enables the simple and rapid development of time-aware nodes for AVB/TSN networks such as automotive Ethernet.

The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.

The WDR core implements an efficient, flexible, low-power and low-latency High Dynamic Range (HDR) and Wide Dynamic Range (WDR) image processor that produces clear and sharp images under any lighting conditions.

The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol.

The TSN-SW implements a highly flexible, low-latency TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and implements the essential TSN timing synchronization and traffic-shaping protocols

The TSN_CTRL implements a configurable subsystem meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards.