CAST, Inc. SoC Catalog

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CAST is a silicon intellectual property (IP) developer, aggregator, and integrator providing IP cores and subsystems since 1993. Our product line features both leading-edge and standards-based digital IP, including compression engines and image processing functions; 8051 microcontrollers and low-power 32-bit BA2Xâ¢ processors; industry-leading automotive interfaces; a complete family of SoC security modules; and a variety of peripherals, interfaces, and other IP cores. Our goal is to maximize IP benefits for our customers by delivering high quality, easy to use, cost effective solutions for real system development challenges. We minimize customer risk through rigorous development standards, complete deliverables with comprehensive documentation, and superlative customer support. We maximize customer value thorough competitive pricing and simple licensingâincluding royalty-free optionsâand long-term partnerships with all leading silicon providers and select technology leaders. Our product standards and business practices have been uniquely honed through successful projects with hundreds of systems designers since the very beginnings of the IP industry, making CAST one of the best IP partners available.

A825-CAN ARINC 825 Avionics CAN Controller

Implements a CAN 2.0 bus controller and provides an application layer that conforms to the ARINC 825 Avionics bus specification.

CAN 2.0 & CAN FD Bus Controller Core

Implements a CAN protocol bus controller that performs serial communication according to CAN 2.0, and CAN FD specifications.

CAN 2.0, CAN FD & CAN-XL Bus Controller

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications.

IEEE 802.1AS Hardware Protocol Stack

The IEEE802_1AS is a complete IEEE 802.1AS hardware stack that enables the simple and rapid development of time-aware nodes for AVB/TSN networks such as automotive Ethernet.

LLEMAC-1G - Low-Latency 10/100/1000 Ethernet MAC

The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.

TSN Ethernet Switch

The TSN-SW implements a highly flexible, low-latency TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and implements the essential TSN timing synchronization and traffic-shaping protocols

TSN_CTRL

The TSN_CTRL implements a configurable subsystem meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards.

SENT/SAE J2716 Controller Core

The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol.

Low-Power, Low-Latency HDR/WDR Image Processor Core

The WDR core implements an efficient, flexible, low-power and low-latency High Dynamic Range (HDR) and Wide Dynamic Range (WDR) image processor that produces clear and sharp images under any lighting conditions.

AXI Peripherals Platform for BA2x Processors

It serves as a basic platform for the rapid development of a variety of system-on-chip (SoC) applications.The platform is well suited to a variety of BA2x-based SoC designs. It includes an AXI interconnect supporting up to four Masters and eight slaves, and a bridge to the slower APB peripherals bus.

Platform IP for BA22-Based Systems

The platform provides the essential IP cores and infrastructure software needed for systems using processors in the BA2x family. Ready for software development out of the box but also easy to customize and extend, it serves as a basic platform for the rapid development of a variety of system-on-chip (SoC) applications.

BA21 - 32-bit Low-Power Embedded Processor

Implements a 32-bit low-power RISC processor that delivers better performance than most processors of its size. Designed for deeply-embedded systems or as an auxiliary processor in larger systems, it ...

CAST Geon Secure Execution Processor for IoT

The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more cryptographically separated execution contexts for a high degree of security during code execution and for data storage and transfer to and from the processor.

Camera Front-End Processor Core

The CAMFE Core implements a flexible, resource-efficient camera front-end processor that receives raw pixel data from a CMOS or CCD sensor and outputs a video stream ready for display, further processing, or compression.

I2S/TDM Multichannel Audio Transceiver

The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and T...

Lossless & Near-Lossless JPEG-LS Encoder

The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

QOI Lossless Image Compression Core

The QOIE Core is an encoder that implements a highly-efficient, low-power, lossless image compression engine compliant with the Quite OK Image format (QOI) specification, version 1.0. The QOI algori...

QOI Lossless Image Decompression Core

The QOID Core is a decoder that implements a highly-efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0. The QOI algori...

H.264 Encoding Application Platform System

This H.264 Application Platform System integrates multiple IP cores with memory and software on a system prototyping board to enable off-the-shelf execution and evaluation of high-definition video compression.

H.264, High 10 Intra Profile Encoder Core

The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a small silicon footprint-approximately 120K gates a...

Motion JPEG Over IP : HD Video Encoder Subsystem

This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video streaming products. Hardware reference designs and customization services complete the solution.

AES Encrypt/Decrypt Core

The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard.

SHA-384 and SHA-512 Secure Hash Crypto Engine

The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by the FIPS180-4 standard.

MACsec Protocol Engine for 10/100/1000 Ethernet

The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all cipher suites provisioned by the MACsec standard an...

GEON Security Platform

The GEON™ Security Platform, the essential suite of hardware security IP, is the natural response to support design teams across a wide spectrum of chip designs and industries.

CAN 2.0 & CAN FD Reference Design

It is a complete reference design for a CAN node subsystem based on the CAN-CTRL CAN 2.0 & CAN FD Bus Controller IP Core. It can be used for evaluating the CAN-CTRL core, and it enables the rapid development of CAN FD applications or device prototypes.

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