13 "Memory" Solutions

The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes.

Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
Dual Port SRAM compiler - TSMC 40 nm uLP - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k

EcoXIP Octal xSPI Memory
EcoXiP's blazingly fast performance and low power consumption allows even time critical software to be executed directly out of non-volatile memory, reducing boot time and system cost.

GDDR6 IP Solution
The Cadence® IP Solution for GDDR6 consists of PHY, controller, and Verification IP (VIP) serving very-high-bandwidth memory applications.

Beyond DDR4 - Next-Generation Main Memory
Focused on advancing single-ended signaling technologies to meet the memory system requirements of next-generation computing applications while maintaining compatibility with current industry standard...

Cryogenic Memory
Rambus is researching opportunities to optimize memory and interface solutions for operation at cryogenic temperatures for future generation datacenters. Evolution of the datacenter is driving new mem...

Designed for performance and power efficiency, the GDDR6 PHY enables big data analytics, crypto mining, ADAS, AI, machine learning, and deep learning.

M31 Memory Compiler
M31 memory compilers are with high quality design for customers. M31 provides the memory solutions for density, power, and performance optimization. M31 memory compilers use industry leading techniques to help customers achieve the best SOC projects.

NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure.

NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in the industry.

DDR Memory Controller - OMC
OPENEDGES is the only total memory system IP company providing both DDR Memory Controller (OMC) and On-chip Interconnect IP (OIC) together.

Simple Low Cost SONOS Flash. Available in affordable 90nm foundry process
LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm geometry and supports auto grade temperature and quality.

DDR Memory Subsystem
The DDR memory subsystem (DDR controller, PHY and 10) is critical to the successful operation of an Soc. System performance and field reliability demand that the DDR subsystem implementation offer the highest performance while at the same time offering the highest quality, in combination with a small footprint and minimal power consumption.


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