www.design-reuse-embedded.com
4 "Emulator and Prototyping->Models and Library" Solutions

1
High Level Synthesizable Models for MIPI M-PHY 3.0
M-PHY is a high-speed serial physical interface technology with flexible signal characteristics and high bandwidth capabilities, which is particularly developed for mobile applications that offer incr...

2
LPDDR4 DRAM Bus Monitor
This is implemented as per JDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system.

3
LPDDR4 DRAM Memory Model
This model is implemented as per JEDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system.

4
UFS 2.0 VIRTUAL PROTOTYPE MODEL
Universal Flash Storage (UFS) is a next generation high-performance NAND Memory Controller to improve the data transfer speed between the Host Processor and the Memory inside a Smart phone, Tablet dev...

 Back

Partner with us

 

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2020 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.