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FlexWay is for design teams who use multilayer AHB but are looking for a scalable solution to address their future needs and automation of interconnect generation. FlexWay uses area optimized interconnect components to address the specific needs of a smaller class of SoC, such as the ability to use common resources to connect several initiators or targets together. The FlexWay architecture has been designed to be 100 percent compatible with the AMBA standard but adds a performance improvement for designs that will benefit from increased performance, but do not warrant a conversion to AXI. For design reliability FlexVerifier automatically verifies the interconnect and generates performance reports and interface protocol coverage.


  • Quick and easy development means faster time-to-market:
  • Pin-to-pin replacement for existing multilayer bus-based solutions.
  • Supports mixed AHB, APB, and simple OCP targets.
  • Supports performance-for-area tradeoffs.
  • Multiple synchronous or asynchronous clock domain support.
  • Insures reliable convergence in synthesis and backend layout phases: supports any backend flow in deep submicron silicon technologies 90 nm and smaller.
  • Unlimited growth and scaling of design complexity, and easy migration to FlexNoC, if desired.


  • Specification capture in FlexArtist with easy, spreadsheet-like user interface.
  • Supports up to four equivalent AMBA layers. Maximum 64-bit data width, AHB and APB cluster initiators with up to 8 initiator sockets per equivalent layer.
  • Supports up to 4 clustered targets with a maximum of 32 sockets per cluster. Maximum 64-bit data width, APB versions 2 and 3, AHB, and simple OCP (no thread, no tag).
  • Memory map and connectivity configuration.
  • Supports security, modes, and user-bit extensions.
  • Automatic instantiation and configuration of FlexWay hardware library components based on specification, topology, and performance parameters.
  • Clusters implemented as AHB Lite, APB, or OCP buses, for best possible area.
  • Automatic synthesis of NoC packet format, address translation, and routing tables.
  • Fixed packetization (no header penalty) automatic serialization changes and clock domain adaptation.


  • FlexWay specification
  • FlexWay architecture capture
  • FlexWay structural synthesis
  • FlexWay verification
  • FlexVerifier VMM (optional)

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