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The AndesCore N7, a family of small cores serves applications including embedded processing devices that require low energy consumption, such as controllers for touch screen, storage, hand-held devices, sensors, and for network connectivity applications like loT (Internet-of-Things).

The N7’s ultra-low power consumption and small size was created for performance constrained SOC designs. The N7’s features the latest AndeStar V3m architecture and a 2-stage pipeline that helps delivering an impressive 168 DMIPS/mW, >40% better than competitive products. Its FlashFetch technology can boosts higher latency flash memory performance without consuming added power. The AndesCore N7 can be as small as 12K gates. This makes it an ideal alternative to 8051 and other 8-bit processor cores, while delivering the programmability benefits of a 32-bit processor solution.

  • Seamless migration to full 32-bit environment from 8/16-bit MCUs
  • Low power consumption for extended battery life
  • Small footprint with low gate count and high code density
  • Speed-up and power reduction for Flash accesses by FlashFetch technology


AndeStar V3m Architecture
  • Better performance for modern compiler
  • Smaller die size and lower power consumption
  • Smaller code size
  • Faster SW development and easier maintenance
  • More performance
  • Quick identification of interrupt sources and fast assignment of service routines
  • Less address bits option leading to small gate count
  • Easy to program and friendly to compiler
CPU Core
  • Superior performance-per-MHz
  • Superior performance-efficiency, while allowing for high speeds
  • More performacne
  • Smaller size
  • Stack size determination and runtime overflow error detection
  • Simplification SoC design and debugging
  • Program code performance tuning
  • Slow flash memory acceleration and power consumption reduction
  • Lower power
  • Simplified SoC integration
  • Faster context switch for real-time applications
  • Better performance-efficiency
  • Peak power consumption reduction
Memory Subsystems
  • Higher efficiency for program execution
    • Flexible size selection to fit diversified needs
    • Capable of replacing DLM and bus for lower cost
    • Capable of replacing bus for lower cost
  • User-selectable bus interface for optimal efficiency


Internet of Things (IOT) Sensor fusion Smart energy monitor and control Home security and remote control Gas/water/electronic metering Medical device Wearable device Education device

Block Diagram


AndeStar V3m Architecture

  • 21st-century RISC-like instruction set
  • V3 subset for MCU most frequency used instructions
  • 16/32-bit mixable opcode format
  • All-C Embedded Programming
  • Hardware divider
  • Direct support of up to 32 interrupts with programmable priority levels
  • 16MB/4G address space
  • Memory mapped IO

CPU Core

  • 1.71 DMIPS/MHz*
    3.36 CoreMark/MHz
  • 2-stage pipeline
  • Choice of multipliers
    • Fast (1 cycle) for performance
    • Small (<0.5K gates) for size
  • Hardware stack protection
  • Processor state bus
  • Performance monitors
  • Interface to FlashFetch IP (separately licensable) which contains following options
    • Prefetching functionality
    • Caching functionality
    • SPI interface to external flash
  • Extensive clock gating and logic gating
  • N:1 core/bus clock ratios
  • Low-latency vectored interrupt
  • Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses
  • PowerBrake technology

Memory Subsystems

  • Optional External Instruction and Data Local Memory
    • Size: 0KB to 4MB
    • ILM: program code, data and IO
    • DLM: program data and IO
  • BIU supports AHB-lite or APB

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