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All Silicon IP All Verification IP


This Cadence® Memory Model Verification IP (VIP) supports the JEDEC® Low Power Memory Device, LPDDR4 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for LPDDR4 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The LPDDR4 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. LPDDR4 Low Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smart phones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.

The Cadence Memory Model for LPDDR4 supports JEDEC LPDDR4X standard. The LPDDR4X memory saves additional power by reducing the I/O voltage to 0.6V from 1.1V. Other LPDDR4X improvements include a single-channel die option for smaller applications, new MCP, PoP, and IoT packages, and additional definition and timing improvements.


  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Comprehensive assertion library: Includes a large number of assertions for assertion coverage
  • Ability to check for errors and change error severity
  • Error injection during Write, Write FIFO, and CA Training
  • Fine-grained control for read and write DQS skew for both channels
  • Pseudo registers for model state, bank state, and initialization state, which can be read anytime though backdoor access to know the device state
  • Randomization of the read output delays
  • Transaction and memory callbacks for all protocol and device memory events (Read/Write)

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