Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Verification Platform  > Simulation and Verification
Online Datasheet        Request More Info
All Silicon IP All Verification IP


The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.

OpenCAPI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env


  • Faster testbench development and more complete verification of OpenCAPI designs.
  • Easy to use command interface simplifies testbench control and configuration of Host and Device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram


  • Implemented in Unencrypted OpenVera, Verilog, SystemC and SystemVerilog.
  • Compliant with OpenCAPI Specification versions 3.0 and 3.1
  • Complete OpenCAPI Tx/Rx functionality.
  • Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.
  • Supports PHY initialization.
  • Supports DL training sets.
  • Supports Deskew markers.
  • Supports Endpoint link speed discovery.
  • Supports Virtualization.
  • Supports AFU packets.
  • Supports DLX packets.
  • Supports DL packets.
  • Supports Command ordering.
  • Supports Translation ordering.
  • Supports Write fragmentation 64-, 128-, 256-byte write operations
    • Partial write operations
    • 64-, 128-, 256-byte write operations
  • Supports scrambler as in OpenCAPI specification.
  • Scrambler can be enabled or disabled.
  • Supports insertion of scrambler errors.
  • Supports 64B/66B line encoding and decoding.
  • Detects and reports the following errors
    • Scrambler errors
    • Under and oversize frame
    • CRC errors
    • Framing errors
    • ACK errors
    • Encoding/Decoding errors
    • Training pattern errors
  • Glitch insertion and detection.
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Supports constraints Randomization.
  • Status counters for various events on bus.
  • Supports bus accurate timing and timing checks.
  • Callbacks in Host, Device and Monitor for user processing of data.
  • OpenCAPI Verification IP comes with complete test suite to test every feature of OpenCAPI specification.
  • Functional coverage for complete OpenCAPI features.

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.