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Body *	<p><strong>Cambridge, MA – March 20, 2025</strong> – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, has announced Platypus<sup>TM</sup>, the world’s first open-standard <a href="https://semiiphub.com/ip/compute-acceleration/efpga" data-cke-saved-href="https://semiiphub.com/ip/compute-acceleration/efpga">eFPGA IP</a> product.</p> <p>Platypus is the FIRST and ONLY commercial eFPGA IP products with:</p> <ul> <li>100% open and standardized FPGA architectures</li> <li>100% open source FPGA bitstream formats</li> <li>100% open source FPGA development tools</li> </ul> <p><strong>The Problem</strong></p> <p>Obsolescence is a critical issue for FPGA-based systems within aerospace, defense, healthcare, communications, automotive, and industrial applications, where lifespans range from 10 to 50 years. For instance, consider the development of the F-35 fighter jet, which began in 1997 and didn’t enter full production until 2021. During this period, transistor density increased by a factor of 10,000X, and the FPGA industry introduced six new generations of architectures.<sup>1</sup> This mismatch between the relentless pace of semiconductor advancements and slow infrastructure development cycles has led to an estimated $50B–$70B in obsolescence-related NRE costs for the US military with 15% of all replacement semiconductor parts being counterfeit.<sup>2</sup> <sup>3</sup></p> <p>Since the inception of FPGAs in the 1980s, commercial FPGA products have become increasingly complex, less standardized, and more opaque<sup>4</sup>, exacerbating issues related to parts obsolescence and counterfeiting. In the best case, an end-of-life notice for an FPGA device or eFPGA IP core necessitates a complete subsystem redesign. In the worst case, it may result in the termination of an entire program.</p> <p>The logical next step in addressing the FPGA obsolescence and counterfeit problems is to move away from single source parts and establish a set of open-standard FPGA architectures, similar to the successful standards created for memory and passive components.</p> <p><strong>Open FPGA History</strong></p> <p>There have been numerous attempts at opening up FPGAs over the last 25 years. The Versatile Place and Route (VPR) open source FPGA research platform was introduced in 1997<sup><a href="https://www.design-reuse-embedded.com/dr-embedded/servlet/publicSite.news?command=modifyNews&newsID=202503124#user-content-fn-5" rel="nofollow" data-cke-saved-href="https://www.design-reuse-embedded.com/dr-embedded/servlet/publicSite.news?command=modifyNews&newsID=202503124#user-content-fn-5">5</a></sup> and has helped lower the barrier to high-quality, reproducible FPGA research ever since. Unfortunately, VPR has remained solely a research tool, and there is still no fully open RTL-to-bits flow for commercial FPGAs.</p> <p><br /><br /><a href="https://design-reuse.com/sip/?q=efpga" data-cke-saved-href="https://design-reuse.com/sip/?q=efpga">eFPGA IP Cores</a><br /><br /></p> <p>To address the lack of fully open FPGA devices, DARPA funded the OpenFPGA<sup>6</sup> and PRGA<sup>7</sup> FPGA generator research projects in 2018. While these open-source generators facilitated the tape-out of several academic chips, the resulting designs were neither standardized nor commercialized.</p> <p>Taking a different approach to circumvent the issue of opaque FPGAs, numerous efforts have been made to reverse-engineer commercial FPGAs. However, as FPGA complexity has surged alongside Moore’s Law, this task has become increasingly difficult and costly<sup>8</sup>.</p> <p>Despite these valiant efforts, there is still not a single open and standardized commercial FPGA product in the market as of today.</p> <p><strong>Standardized FPGAs (SFPGA)</strong></p> <p>With the launch of the Platypus eFPGA family, Zero ASIC is making a momentous leap toward standardized FPGAs by openly releasing complete architecture descriptions and bitstream formats of its commercial Z1000 eFPGA IP under an open-source Apache License, with the goal of making it an open standard.</p> <p>Historically open standards have proven to be a highly effective defense against obsolescence and predatory pricing strategies. Notable ubiquitous open hardware standards include the RISC-V ISA, IEEE Ethernet PHYs, JEDEC memories, passive footprints (e.g., 0603, 0805), PCIe, and USB. Just like with RISC-V, creating an open standard does not mean the implementation must be open source. The table below illustrates the similarities between the successful RISC-V ISA standard and the proposed FPGA approach.</p> <table class=" cke_show_border"> <tbody> <tr> <th> </th> <th>RISC-V</th> <th>SFPGA</th> </tr> <tr> <td>Architecture Standard</td> <td>ISA Specification</td> <td>FPGA Arch Specification</td> </tr> <tr> <td>Hardware Source Code</td> <td>Open/closed</td> <td>Open/closed</td> </tr> <tr> <td>Binary Program</td> <td>Executable</td> <td>Bitstream</td> </tr> <tr> <td>Binary Compatibility</td> <td>Yes</td> <td>Yes</td> </tr> <tr> <td>Consortium</td> <td>RISC-V International</td> <td>TBD</td> </tr> </tbody> </table> <p><strong>Impact of Standardized FPGAs</strong></p> <p>The RISC-V ISA started as a humble UC Berkeley research project, with the first specification published in 2011<sup>9</sup>. In 2014, David Patterson and Krste Asanovic made a compelling case for why ISAs should be free, igniting the RISC-V movement<sup>10</sup>. A decade later, RISC-V is now shipping in billions of devices annually<sup>11</sup>.</p> <p><em>“Developing a open-standard FPGA architecture and an ecosystem of standard compliant components will revolutionize FPGA-based system design, much like RISC-V has transformed CPU design. Just like with RISC-V, market dynamics will dicate whether the potential upside of open standards overcomes the status quo inertia of vendor lock-in.”</em> —Andreas Olofsson</p> <p><strong>Product Availability</strong></p> <p>Platypus standard eFPGA IP cores are available today to early access customers. For more information visit <a href="https://www.design-reuse.com/exit/?urlid=59419" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59419">https://zeroasic.com/platypus</a>.</p> <p>The FPGA Architect platform will be available to customers in Q2 2025 on a per project basis. For more information visit <a href="https://www.design-reuse.com/exit/?urlid=59420" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59420">https://zeroasic.com/fpga-architect</a>.</p> <p>About Zero ASIC</p> <p>Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon through chiplets and automation. Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.</p> <p><strong>References</strong></p> <ol> <li> <p>F-35 Lightning II History, <a href="https://www.design-reuse.com/exit/?urlid=59421" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59421">https://www.f35.com/f35/index.html</a></p> </li> <li> <p>McKinsey & Company (2022), <em>How industrial and aerospace and defense OEMs can win the obsolescence challenge</em>, <a href="https://www.design-reuse.com/exit/?urlid=59422" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59422">https://www.mckinsey.com/industries/aerospace-and-defense/our-insights/how-industrial-and-aerospace-and-defense-oems-can-win-the-obsolescence-challenge</a></p> </li> <li> <p>Semiconductor Industry Association (2018), <em>Detecting and Removing Counterfeit Semiconductors in the U.S. Supply Chain</em>, <a href="https://www.design-reuse.com/exit/?urlid=59423" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59423">https://www.semiconductors.org/wp-content/uploads/2018/06/ACTF-Whitepaper-Counterfeit-One-Pager-Final.pdf</a></p> </li> <li> <p>Stephen Trimberger (2018), Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. IEEE Solid-State Circuits Magazine. 10. 16-29. <a href="https://www.design-reuse.com/exit/?urlid=59424" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59424">https://doi.org/10.1109/mssc.2018.2822862</a>.</p> </li> <li> <p>Vaugh Betz and Jonathan Rose (1997), VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications</p> </li> <li> <p>X. Tang, et al (2020), OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs,in IEEE Micro, vol. 40, no. 4, <a href="https://www.design-reuse.com/exit/?urlid=59425" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59425">https://doi.org/10.1109/MM.2020.2995854</a>.</p> </li> <li> <p>Ang Li and David Wentzlaff (2021). PRGA: An Open-Source FPGA Research and Prototyping Framework. FPGA ‘21 <a href="https://www.design-reuse.com/exit/?urlid=59426" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59426">https://doi.org/10.1145/3431920.3439294</a></p> </li> <li> <p>K. E. Murray, et al (2020), SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs, in IEEE Micro, vol. 40, no. 4, pp. 49-57, <a href="https://www.design-reuse.com/exit/?urlid=59427" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59427">https://doi.org/10.1109/MM.2020.2998435</a></p> </li> <li> <p>Andrew Waterman, Yunsup Lee, David Patterson (2011), Krste Asanovic, The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA,Technical Report No. UCB/EECS-2011-62 <a href="https://www.design-reuse.com/exit/?urlid=59428" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59428">http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.html</a></p> </li> <li> <p>Krste Asanovic and David Patterson (2014), Instruction Sets Should Be Free: The Case For RISC-V, UC Berkeley Technical Report UCB/EECS-2014-146, <a href="https://www.design-reuse.com/exit/?urlid=59429" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59429">http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html</a></p> </li> <li> <p>RISC-V International (2024), <em>Nvidia to ship a billion of RISC-V cores in 2024</em> <a href="https://www.design-reuse.com/exit/?urlid=59040" rel="nofollow" data-cke-saved-href="https://www.design-reuse.com/exit/?urlid=59040">https://riscv.org/ecosystem-news/2024/10/nvidia-to-ship-a-billion-of-risc-v-cores-in-2024/</a></p> </li> </ol> <p> </p>
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