D&R News Alert
September 17th, 2020
In this issue
• Nvidia's $40 Billion ARM Purchase Will Test Current M&A "Ceiling"
• Taiwan Semiconductor And Samsung Electronics Foundry Business Post-SMIC Blockade
• CEVA Partners with Fluent.ai to Offer Multilingual Speech Understanding Solutions
• MIPI Alliance Releases A-PHY SerDes Interface for Automotive

Welcome to the issue of September 17th, 2020 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Industry’s First JEDEC DDR5 JESD79-5 Verification IP
• Exhaustive protocol checks & spec-linked coverage
• Optimized performance with Verdi debug & performance analyzer
• PHY trainings, board delay & jitter modeling support
• Early adopters in Processor, AI/ML & Cloud
Learn more about Synopsys’ DDR5 collaborations here >>

Around Foundries
Interface IP
Rush to get the Adaptive Body Bias IP, the missing IP for a fast and safe implementation in 22FDX technology

Dolphin Design • Self-contained IP for fast implementation of body bias
• Low power consumption impact: 30 µW in typical
• Up to 10X gain in Energy Efficiency
• Silicon proven to secure your silicon

     ABB IP for IoT applications >>                ABB IP for automotive applications >>
Complete power management platform in 22FDX >>

Adding RISC-V CPU Custom Extensions Can Boost Performance, Reduce Power, and Cut Cost in 5G, AI. AR/VR, and IoT applications

Artificial Intelligence
PUF based Root of Trust PUFrt for High-Security AI Application

Secure AHB Performance Subsystem for Cortex® M3
• Secure AHB Fabric, SRAM and ROM MPUs, QSPI, DMA, PMU
Proven AMBA® controllers, bridges, fabrics, subsystems
Attend upcoming Silvaco SURGE summit on tools and IP

Secure-IC is ready for ASIL B or ASIL D levels projects with its Securyzr integrated Secure Element

D&R Welcomes its New Partner
Nextera NexteraVideo
Provider of FPGA IP cores supporting
• the SMPTE ST 2110
• ST 2059 Video over IP standards
And more >>

Internet of Things and 5G
Webinar Webinar on RISC-V Custom Instruction for accelerators and direct multicore communications for 5G, AI, AR/VR and IoT
When: September 29th 2020 - 8am PDT Register Now
Andes, Imperas and UltraSoc


Meet multi-standard decoder IP, optimized incl. AV1:
  • Supports HEVC/H.265, AVC/H.264, VP9, AVS2, AV1 std.
  • Decoding up to 8K60fps (8Kx4K) resolution at max
  • Packaged with C&M’s proprietary cFrame technology
  • Saves 50-80% bandwidth usage

What they said at
IP SoC China 2020

IP Solutions Advancing AI/ML Performance
Wangyang Cao, Applications Engineer IP Cores, Rambus Inc.

Camera and Display IP for Mobile & Automotive in the Era of AI/5G
Kelvin Xu, IP Product Marketing Manager, Synopsys, Inc.

Next-generation Endpoint AI with the new Arm Cortex-M55 processor
Derek Xi, Strategy Director, Arm

VeriSilicon IP based High Performance Video Transcoding Chip and Open Source Software Solution
Wiseway Wang, VP, GM of System Platform Solution Division, Verisilicon

High Performance Sensor Hub DSP Architecture for multiple sensors and Edge AI
Benjamin Ye, Software Field Application Engineer, CEVA, Inc.

MIPI PHY in FDSOI Technology
Jintao Zang, Senior Mixed-Signal Design Engineer, Mixel, Inc.

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