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TSMC Steps Through 7, 6, 5, Moore
Moore’s law countdown delivers process, package advances
By Rick Merritt, EETimes
April 24, 2019
SANTA CLARA, Calif. — TSMC added an N5P process and more details on advanced packages to its roadmap for squeezing advances from silicon at an annual event here.
tsmc IP Cores
At the bleeding edge, picking a path forward among expanding 7, 7+, 6, 5, and 5+ options is increasingly complex. “The good news is we continue to see scaling for the foreseeable future,” Yuh-Jier Mii, a senior vice president for technology development for TSMC, told an audience of about 2,000 attendees.
Even chief executive C.C. Wei cracked a joke over TSMC’s news last week of a 6-nm option that will start risk production a year after its previously announced 5-nm node. “I had to ask my R&D people what their thinking was — was that for fun?” he quipped in a keynote. “Next time, you won’t be surprised if I release an N5.5.