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Andes Launches First DSP Instruction Set for RISC-V Multi-Core Processors to Challenge the HPC Marke
By Korbin Lan - TAIPEI, Taiwan, Apr. 22, 2019 –
Leading up to the RIC-V forum, RISC-V CON, which will be held in Hsinchu on May 9, Andes Technology Corporation on April 19 hosted an explanatory press conference for new processor products and ecosystem services. Their new products will include the first RISC-V processor of its kind with a DSP instruction set (A25MP/AX25MP), which can provide more than twice the operating performance of their competitors, and it is a computational tool for handling artificial intelligence applications.
Andes Technology President Frankwell Jyh-Ming Lin stated that RISC-V architecture is equipped with command streamlining, which has the advantages of being modular and expandable, considerably facilitating development and ease of deployment. Furthermore, because RISC-V is an open source directive, developers are permitted to add to or modify it in accordance with their own requirements. Therefore, it has better design flexibility and will consequently gradually be favored by developers.
On the other hand, owing to the rise of AI and IoT trends, uniform specifications will no longer be pursued in product development, and more customization and differentiation will instead be sought out. As a result, this will motivate designers to move to more flexible RISC-V architectures and bring about an RISC-V boom.
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