An Introduction to the RISC-V-Based SweRV Core

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This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

allaboutcircuits.com, May. 15, 2019 – 

Since the RISC-V instruction set architecture was unveiled (2015) and RISC-V foundation established (2016), we have seen a flurry of activity: many open source hardware projects, many corporate adoptions of the architecture, fast-growing membership of the foundation, and fast-growing open-source RISC-V software activity.

At the "Core" of all these projects are RISC-V CPU (Central Processing Unit) cores – hardware engines that are executing RISC-V compiler binaries. All community stakeholders benefit from the open-source software, including common compilers, toolchains, and operating systems that can execute on top of these cores.

Some of the RISC-V cores developed are proprietary (or available for IP licensing), but even more are available in the open-source domain. The availability of open-source RISC-V cores enables a large number of fully open-source hardware projects, including educational purposes and unprecedented hardware level collaboration and innovations, which otherwise would not be possible.

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