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Wireless 3D Integration – Making Stacking Silicon as Easy as Stacking Lego (1/2)

community.arm.com, Nov. 06, 2019 – 

Over the past few years, the growth of the Internet of Things (IoT) has brought about a range of new challenges for IC designers. IoT devices are required to perform a range of different functions. These range from; analogue sensing and energy-harvesting, to digital processing and wireless communication), all within very strict power and volume constraints. To manage this, it is becoming commonplace that integration of these different components happens within the chip. Often, however, each component requires its own silicon process technology, so combining these different elements is not a straightforward task.

One solution to this challenge is fabricate each die in its own process technology, and then stack them up. This is known as '3D integration'. Figure 1 shows an example of such a 3D stacked IC. The design of each of the stacked tiers is understood. In addition, to physically build this chip, a way of communicating the data vertically through the system (as illustrated by the arrows in Figure 1) is also required.

To do this, most of the research community are focusing on the development of through silicon vias (TSVs). TSVs are metal pillars, etched entirely through each silicon die, to provide electrical connectivity with neighbouring tiers. TSVs promise high density, high bandwidth communication and are already being deployed in some high-end commercial memory stacking applications. However, designing with TVSs is expensive. The fabrication and assembly processes used in TSV-based 3D-IC manufacture are only available in the very latest technology nodes. These vary from foundry to foundry. IoT devices are supposed to be ubiquitous, low-cost and disposable. This makes incorporating the high-cost technology unfeasible.

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