RISC-V Not So Risky

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RISC-V has come a long way but the open source instruction set still has to fight among giants.

electronicdesign.com, Nov. 19, 2019 – 

RISC-V is a true reduced instruction-set computing (RISC) platform. The standard defines a modular, open-source, instruction set architecture (ISA) that can be extended from an integer-based, 32-bit microcontroller through a multicore, virtual-memory, virtual-machine core that can take on high-end computing chores. It competes with the likes of Arm, Intel, and MIPS, although this newcomer has a lot of ground to make up in a very long race.

The ISA is based on 32-bit instructions, but it doesn't have condition codes. Instead, it uses register-based comparison branching instructions. There's a register file with 32 registers, although register 0 contains a value of zero. The system can be configured with 16-, 32-, 64-, and 128-bit registers.

RISC-V doesn't have a hardware stack. A jump-and-link (JAL) instruction copies the program counter to a register, allowing a software stack to be implemented as needed. The advantage to this approach is that different stack implementations are possible.

RISC-V doesn't define an implementation, rather only the instruction set and virtual architecture. A naming convention helps define what's encompassed by a particular implementation.

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