Lattice Semiconductor launched new low-power FPGA based on FD-SOI

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simmtester.com, Dec. 17, 2019 – 

Lattice Semiconductor has launched a new FPGA technology platform for its low-power FPGAs based on 28nm fully depleted silicon-on-insulator (FD-SOI) process technology. The company also announced its first FD-SOI product, CrossLink-NX.

Lattice announced its intention to transition to FD-SOI for new products a couple of years ago, in order to take advantage of the process technology's inherent strengths in power consumption and reliability. The company's Nexus FD-SOI platform continues its focus on small form factor, low power FPGAs, and is optimized for devices with 10-200k logic cells.

"We are using Nexus to enable the development of some FPGA families that provide up to 75% reduction in power compared with competing families, are 100 times more reliable in terms of soft error rate, are able to deliver the smallest form factor. They have some of the performance features that we see people are needing in high performance edge computers," said Gordon Hands, director of product marketing, Lattice Semiconductor.

The Nexus platform is based on the 28nm FD-SOI process at Samsung Foundry. Moving forward, this platform will be used to develop new products more quickly, since it allows design reuse and lowers development cost, Hands said. Nexus includes system-level solutions that combine design software and pre-engineered soft IP blocks with evaluation boards, kits and reference designs.

Nexus' architectural features include optimized DSP blocks and higher on-chip memory capacity that enable the higher memory to logic ratios demanded by edge AI applications. Nexus devices "run twice as fast at half the power" compared to previous generations of Lattice devices, the company said.

FD-SOI reduces devices' power consumption since its buried oxide layer reduces parasitic capacitance and leakage. The substrate can also be biased (back-biasing), which increases the threshold voltage of devices. Back-biasing reduces switching speed but drastically reduces leakage currents; speed can be traded off with power consumption in this way.

Soft error rate (SER), a known problem for SRAM based FPGAs built on bulk silicon, is also minimized since the buried oxide layer separates the active circuitry associated with the transistor from the substrate. The area susceptible to particle strikes (marked orange in the diagram above) is vastly reduced. On Lattice's Nexus platform, the SER is typically reduced by a factor of 100. This reliability is critical to applications such as automotive and industrial.

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