RISC-V reference models support processor verification

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microcontrollertips.com, Feb. 25, 2020 – 

Imperas Software Ltd., announced the latest enhancements to its range of RISC-V reference models and solutions to support processor verification, with the leading commercial SystemVerilog hardware design verification environments provided by Cadence, Mentor, Synopsys, and also the Metrics cloud-based tools. Working together with lead customers, industry groups and associations, and the Google Instruction Stream Generator (ISG) developers, Imperas has enhanced the OVPsim reference models to support the comparison with directed tests, the RISC-V Foundation's compliance tests, and tests created by the open source Google random ISG. The new approach to encapsulate the reference models within a SystemVerilog UVM (Universal Verification Methodology) test bench to allow a side-by-side comparison (step and compare verification) of RTL and reference model within the same environment for an interactive transaction-based analysis.

With this new release, hardware developers can for the first time use a golden reference model of a RISC-V processor alongside their RTL in their SystemVerilog UVM design verification (DV) environments.

The traditional view of the SoC design flow typically estimates that between 40 percent to 70 percent of the time and effort is directed at verification tasks. Based on the assumption of "known-good" semiconductor IP cores, the SoC verification is focused almost completely on the unique value-added features outside of the cores. Now with RISC-V, SoC developers can enjoy the additional design freedoms of an open ISA and explore options for customized, optimized instructions and extensions. In addition, the latest many-core SoCs can now utilize a broad range of individually optimized cores, each tailored to the rightsize requirements. Verification at the RISC-V core level is now an essential task for any SoC design with a custom processor, or custom instructions.

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