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Neural net accelerates IC design placement

Google has come up with a neural net that can do IC design placement in record quick time.

electronicsweekly.com, Mar. 24, 2020 – 

"We have already seen that there are algorithms or neural network architectures that don't perform as well on existing generations of accelerators, because the accelerators were designed like two years ago, and back then these neural nets didn't exist," says Google's Azalia Mirhoseini, "if we reduce the design cycle, we can bridge the gap."

After studying chip designs, the neural net can produce a design for a Google Tensor Processing Unit in less than 24 hours that beats several weeks-worth of design effort by human experts in terms of power, performance, and area.

Placement is so complex and time-consuming because it involves placing blocks of logic and memory or clusters of those blocks called macros in such a way that power and performance are maximized and the area of the chip is minimised.

Heightening the challenge is the requirement that all this happen while at the same time obeying rules about the density of interconnects. Anna Goldie and Mirhoseini targeted chip placement it takes a human expert weeks of iteration to produce an acceptable design.

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