The Increasingly Ordinary Task Of Verifying RISC-V

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semiengineering.com, Jun. 03, 2020 – 

As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself.

So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this task scales up with multiple cores and the addition of off-the-shelf peripherals and custom hardware modules. And as with any processor core, it's just as complex and time-consuming of a project.

"We can see two verification challenges here," said Zibi Zalewski, general manager at Aldec's Hardware Products Division. "First is the complexity of the core itself and how to make sure it is correct and ISA-compliant. Second is how to test the system using the core. In both cases, transaction-level hardware emulation is the perfect choice – particularly if the emulation is based on the Accellera SCE-MI standard, which allows for reusability between different platforms and vendors. Combined with automatic design partitioning and wide debugging capabilities, this makes a complete verification platform."

When the processor core becomes more powerful and brings in more functionality, RTL simulation is not enough. Nor does it provide complete test coverage in a reasonable time. With emulation, the speed of testing is much faster. That, in turn, allows the complexity and size of the tests to be increased, along with cycle accuracy, without extending the time

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