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Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5

semiwiki.com, Sept. 09, 2020 – 

This is another installment covering TSMC's very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC's vast ecosystem collaborates with each other and with TSMC. The talk covered here focuses on a complete on-die clock subsystem for PCIe Gen 5. Alan Rogers, president and CTO of Analog Bits, provided detail and motivation regarding the need for on-chip clock support to facilitate high-performance communication subsystems.

A memorable quote from Alan was "we will discuss how to synchronize the serial data interfaces which can move tens of billions of bits of data each and every second on and off a chip through a pair of wires."

Alan began with a historical perspective on data communications. He pointed out that historically a SerDes would be supplied with a discrete clock chip, provided on the PCB. This worked fine when the SerDes had a limited number of high-end lanes that were not cost constrained. He went on to explain that today, there are a very high number of SerDes lanes and clock synchronization off-chip becomes very difficult to achieve. Performance demands are simply inconsistent with inter-chip transmission of remote clock sources. The system constraints in terms of dollars, power or pin count preclude a non-integrated solution.

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