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First steps to European multicore RISC-V chip for space

The De-risc project has shown the first milestones for a purely European multicore RISC-V processor for satellite, spavce and HAPS designs

www.eenewseurope.com, Nov. 16, 2020 – 

The first steps to a European version of a RISC-V multicore processor design for space and aerospace applications have been demonstrated.

The three year, €3.4m De-Risc project is part of the European Horizon 2020 programme. It brings together Thales, Cobham Gaisler, the Barcelona Supercomputer centre and software house FENtiss to develop open source hardware and software for space applications as well as high altitude pseudo-satellites (HAPS). These are drones or balloons that fly at altitudes over 20km for surveillance, monitoring and cellular basestations.

By March 2020 the project aims to deliver a full, European-sourced Integrated Modular Avionics hardware and software platform.

In the first year, the project has developed the first version of the De-RISC MPSoC platform and the Performance Monitoring Unit, integrating observability (Cycle Contention Stack, Request Duration Counter) and controllability capabilities (Maximum-Contention Control Unit) for a fault tolerant design.

Cobham Gailer in Sweden has extensive experience in the area, having developed the widely used LEON processor, which is based around the SPARC V8 architecture. The following LEON2 processor was designed under contract from the European Space Agency, and is available as a radiation-hardened chip from Microchip as the AT697 and AT791. The project is using Gailer's NOEL-V (LEON backwards) existing 64bit RISC-V processor in VHDL that shares many elements with the latest LEON5 core as the basis for the multicore design.

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