ARM pushes chiplets and 3D packaging for Neoverse chips

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By Nick Flaherty, eeNews Europe (April 27, 2021)

ARM has launched an enhanced mesh interconnect IP for its high performance Neoverse processor cores that enables more use of chiplets and 3D packaging.

Chiplets allows separate chips to be used in the same package to provide high speed data links or stacked memory. The CMN-700 supports 144 end points for 128 cores plus chiplets and memories, rather than the limit of 64 for the previous CMN-600.

“CMN-700 [is] a key element for constructing high-performance Neoverse V1 and Neoverse N2-based SoCs,” said Chris Bergey, SVP and GM, Infrastructure Line of Business at ARM. “Platform IP is essential which is why we developed the CMN700 mesh interconnect with DDR5 support and multichip capabilities,” he said. “It adds CXL to build host or end point devices and the the other key multichip upgrade was for multi-die and chiplet integration and this will open new doors and allow more flexibility,” he said.

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