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Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon

Samsung and Cadence co-develop Mixed-Signal OpenAccess-ready PDKs that enable seamless implementation and verification of mixed-signal designs for data centers, networking, 5G, mobile, industrial and automotive applications

www.cadence.com, Sept. 08, 2021 – 

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has collaborated with Samsung Foundry to deliver qualified Mixed-Signal OpenAccess-ready process design kit (PDK) technology files that support a range of Samsung process technologies from 28FDS to GAA base 3nm. The Mixed-Signal OpenAccess-ready PDK allows mutual customers to speed their time to market by ensuring that the qualified Cadence® custom and digital design tools seamlessly interoperate on various Samsung process technologies. The Mixed-Signal OpenAccess-ready PDK improves productivity for mixed-signal designs used in data centers, networking, 5G, mobile, industrial and automotive applications.

The Cadence digital tools included with the Mixed-Signal OpenAccess PDK for Samsung process technologies are the Innovus™ Implementation System, Genus™ Synthesis Solution, Liberate™ Characterization Suite, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ Extraction Solution, Physical Verification System, Tempus™ Timing Signoff Solution, Voltus™-Fi Custom Power Integrity Solution, and Litho Physical Analyzer. The Cadence custom tools included in the PDK are the Virtuoso® ADE Product Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre® X Simulator, and LDE Electrical Analyzer.

Using the Mixed-Signal OpenAccess-ready PDK with the Virtuoso and Innovus platforms, customers can seamlessly access mixed-signal designs in a common OpenAccess database. This co-design methodology promotes shared responsibilities and collaboration between the analog and digital teams for chip planning, design, implementation, physical verification, and signoff, improving overall productivity and increasing design throughput.

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