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Axiomise Unveils Intelligent Debug Solution for Formal Verification of RISC-V Cores

Jan. 03, 2022 – 

Identified 30 new bugs in WARP-V Family when Paired with Axiomise Formal App

LONDON –– January 3, 2022 –– Axiomise, the leading provider of cutting-edge formal verification consulting, training, services, and IP, today launched the industry’s first intelligent debug solution for formal verification of RISC-V cores.



RISC-V IP Cores

Intelligent Rapid Analysis Debug and Reporting (i-RADAR) is available as a plugin in the Axiomise formalISA app that provides a complete end-to-end vendor-neutral formal verification solution for architectural validation of RISC-V cores. i-RADAR and formalISA were used to formally prove three new RISC-V cores from the WARP-V family.

“The formalISA app combined with i-RADAR found new bugs not previously found by other verification solutions,” remarks Dr. Ashish Darbari, CEO and founder of Axiomise and one of the foremost authorities in practical applied formal verification.

Axiomise also created a new formal verification solution for security verification of RISC-V cores and used it to identify several security vulnerabilities in multiple RISC-V cores. A paper describing the solution titled, “Comprehensive Processor Security Verification: A CIA problem,” will be presented in Design Automation Conference’s virtual format the week following in-person DAC.

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