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RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021

Jun. 21, 2022 – 

Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design.

Nuremberg, Germany – June 21, 2022RISC-V International, the global open-design standards pioneer, announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension. The news builds on momentum from 2021, in which 16 specifications representing more than 40 extensions were ratified.

“The RISC-V culture of contribution and collaboration continues to produce impressive and strategic results,” said Calista Redmond, CEO of RISC-V. “RISC-V members are leaders in the era of open compute, proving that collaboration accelerates innovation through shared investment while growing global opportunity.”

“These new specifications accelerate embedded and large-system design,” said Mark Himelstein, CTO of RISC-V. “Debugging is one of the hardest things to do on a chip,” he explained. “E-Trace for RISC-V creates a standard way to do processor trace that’s extremely efficient and is especially useful in embedded system design.”

“RISC-V SBI offers developers a similarly critical resource,” Himelstein added. “The ability to port supervisor-mode software across all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere.”

“UEFI is a critical element of any system,” said Himelstein, “In some applications, it may replace basic BIOS software.”


“For many microcontroller applications, division operations are too infrequent to justify the cost of divider hardware,” explained Himelstein. “The RISC-V Zmmul extension will benefit simple FPGA soft cores in particular.”

RISC-V announced the ratifications at Embedded World here, where RISC-V is the focus of several talks. RISC-V International is also hosting a pavilion of member-company innovations in the exhibition hall through June 23rd. Showcase participants include Andes Technology; CAES, Cobham Gaisler; Canonical Ubuntu; Codasip; Codeplay; Digital Core Technologies; GreenWave Technologies; Imperas; OpenHW Group; SiFive; Syntacore and Ventana Micro Systems.

About RISC-V International

RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. More than 2,800 RISC-V members across 70 countries contribute and collaborate to define RISC-V open specifications as well as convene and govern related technical, industry, domain, and special interest groups. RISC-V combines a modular technical approach with an open, royalty-free license model — meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V. RISC-V enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation. To learn more, visit www.riscv.org.


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