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RISC-V International emits more open CPU specs

Embedded World RISC-V International has grown its pile of royalty-free, open specifications, with additional documents covering firmware, hypervisors, and more.

Prague, Jun. 22, 2022 – 

RISC-V – pronounced "risk five", and not to be confused with the other architecture of that name, RISC-5 – essentially sets out how a CPU core should work from a software point of view. Chip designers can implement these instruction set specifications in silicon, and there are a good number of big industry players backing it.

The latest specs lay out four features that compatible processors should adhere to. Two of them, E-Trace and Zmmul, will be useful for organizations building RISC-V hardware and software, and the other two could prove important in future, aiding the development of OSes to run on RISC-V computers.

One of these is the UEFI boot protocol that specifies how system firmware obtains and handles information about the hardware before loading an OS kernel. Another defines a Supervisor Binary Interface (SBI) between the hardware and an operating system or hypervisor kernel, complete with a reference implementation by Western Digital called OpenSBI.

RISC-V International CTO Mark Himelstein said this was a "critical resource," offering "the ability to port supervisor-mode software across all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere."

As for the others, the E-Trace specification allows for efficient processor-branch tracing on RISC-V devices. If that's your sort of jam, there's a 100+ page PDF on GitHub.

The Zmmul extension specifies multiplication math support, with no division, primarily for small and simple embedded cores – there are already separate extensions for integer and floating-point math, including multiplication and division, for general-purpose...

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