D&R News Alert
August 26th, 2024
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Welcome to the issue of August 26th, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Join Us at the Processor IP Summit 2024!
Synopsys
• Power-efficient RISC-V, DSP & NPU IP Solutions
• PPA Differentiation in SoC/Chip Design
• Cutting-edge Tools: AI, Automotive Safety, SW Development

Register now >>

Foundry News
Samsung’s new 2 nm foundry process to cut chip size by 17%
Design Platform
Optimizing Analog Layouts: Techniques for Effective Layout Matching
Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for HPC and AI Infrastructure
Memory Standard
JEDEC Releases New Standard for LPDDR5/5X Serial Presence Detect (SPD) Contents
Interface IP

New ! PCIe 7.0 PHY for TSMC N5 by Synopsys
PCIe 7.0 Controller with AXI by Rambus
MIPI DSI-2 RX Controller by Qualitas Semiconductor

Processor IP
Pipelined Data Masters in D-Series GPUs by Imagination
New RISC-V Innovations Lead AI to Open Standard
Artificial Intelligence
Chip design software firm Synopsys delivers record revenue as AI accelerates demand
Cadence Launches Fem.AI, Pledges $20M to Kickstart Gender Equity in the AI Workforce
Why Interlaken is a great choice for architecting chip to chip communications in AI chips by Chip Interfaces
Report says that promise of AI relies on scaling security as edge AI booms
Automotive
intoPIX Solutions Tackle the Biggest Challenges in Automotive Imaging at ADAS & Autonomous Vehicle Expo 2024
Security Solutions
PQSecure Joins the Post-Quantum Cryptography Coalition (PQCC)
Networking
Beyond 5G expect ISAC for Radar Positioning and More
Green Electronics
EU Ecodesign Regulation for the adhesives and sealants industry: key role for circular economy and electronics recycling
What's new about EECONE EU Project ?
Interview with Dr. Golzar Alavi - Bosch
Reducing eWaste from Electrical Control Units for Automotive Industry
during EECONE General Assembly


Business News
Synopsys Posts Financial Results for Third Quarter Fiscal Year 2024







New IP
Power on Reset 1.2V by NTLab
LZ4 compression and decompression IP core by ZeroPoint Technologies
Ultra-low jitter, low-power ring-oscillator-based PLL - 4.5GHz-9.5GHz by InCirT


PCIe 7.0 PHY for TSMC N5
• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 7.0, encoding, backchannel initialization

What they said at
DAC 2024 ?


KH Lee
President of Faraday Americas
Faraday Technology


Anupam Bakshi
Founder & CEO
Agnisys, Inc.


Annamalai Muthu
Director
CM Engineering Labs Singapore Pte. Ltd


Purna Mohanty
CEO
Signature IP Corporation


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