The IEEE802_1AS is a complete IEEE 802.1AS hardware stack that enables the simple and rapid development of time-aware nodes for AVB/TSN networks such as automotive Ethernet. It operates fully autonomously and provides timing and synchronization according to IEEE 802.1AS for full-duplex, point-to-point Ethernet links.

IEEE802.1AS compliant AVB/TSN stack is part of the line of automitive IP cores from CAST, Inc.The core is designed to operate next to an Ethernet Media Access Control unit (eMAC) and attached to that eMAC s data-interface towards the host system. It automatically synchronizes its internal real-time clock (RTC) to that of the grandmaster by inserting and extracting IEEE 802.1AS frames in and from the Ethernet traffic. The core fully offloads the host processor from any IEEE 802.1AS related processing, and at the same time enables the development of time-aware applications: it provides timestamps, periodic event triggers, and alarms to the host system, using host processor Interrupt lines or dedicated-low latency interface signals.

The core uses standard AMBA® or Avalon® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit wide AXI4-Lite or Avalon-MM bus, and Ethernet frame packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses. Furthermore, the core causes no constraints with respect to system clocking, as it assumes separate and independent clocks for each of its interfaces (i.e., host, tx data, and rx data), and separate and independent clocks for its RTC and internal timers. To further ease integration, the core is available pre-integrated with either Altera s or Xilinx s eMAC cores. Integration with other 3rd party eMAC cores is also possible using CAST design integration services. Complete reference designs on commercially available FPGA boards are also available, and can be used for on-field testing or as templates to speed-up application development.

The IEEE802_1AS core is designed with industry best practices. The design is CDC-clean, LINT-clean, and scan-ready. The core is available in synthesizable RTL (Verilog 2001) source code or as targeted FPGA netlists. Deliverables provide everything required for a successful implementation, including sample scripts, a testbench, and comprehensive documentation.