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Semu Emulator


Are simulators too slow to fully verify today s complex IP blocks and subsystems? Are corner cases too difficult to reach? Are running real data and full regressions next to impossible? Emulation and FPGAs promise high-speeds, While they are a little bit expensive and difficult-to-use. Semu emulator was researched and developmented based on the concept of emulation performance at simulation price , It breaks the functional verification bottleneck by delivering the high-speed of FPGA-based emulation without compromising debug visibility and control.

Semu emulator is based on the SCE-MI protocol, FPGA, BSV language and BSC compiler. It can bring up data interaction channels between the upper software control layer and the underlying algorithm logic implemented on FPGA rapidly. And, It can quickly realize C and Verilog mix Test. compilation, rapid mapping with flexible software control mapping running on PC and accelerated logical mapping algorithm running on the FPGA.

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