www.design-reuse-embedded.com
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Verification Platform  > Emulator and Prototyping->Models and Library  > Models and Library

LPDDR4 DRAM Bus Monitor

Overview

LPDDR4 DRAM Bus Monitor is implemented as per JDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system. It is a part of Arastu s comprehensive low power verification suite which also includes LPDDR4 DFI PHY Functional Model and LPDDR4 DRAM Memory Model.

Partner with us

 

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2020 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.