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LPDDR4 DRAM Bus Monitor is implemented as per JDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system. It is a part of Arastu s comprehensive low power verification suite which also includes LPDDR4 DFI PHY Functional Model and LPDDR4 DRAM Memory Model.


  • Support for LPDDR4 memory devices from all leading vendors
  • Supports multiple device densities: 4Gb to 32Gb
  • Supports capturing of all the valid LPDDR4 commands as per the JESD209-4A specifications
  • Reports DRAM bus utilization in different formats
  • On-the-fly protocol and data checking
  • In-built virtual memory support to detect data corruption from DRAM devices
  • Clock Stop and Dynamic frequency change to any valid DDR operating frequency
  • Provides guidance to Memory Controller to improve bus utilization (through Performance Predictor)
  • Supports Target Row Refresh (TRR) and Post Package Repair (PPR)
  • Supports Data Bus Inversion (DBI) and Data Mask (DM)
  • Available in pure SystemVerilog to facilitate seamless integration in any verification environment

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