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The Veloce verification system reduces project schedules and cost through high-performance simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits through a unique architecture and best-in-class technologies.


  • Acceleration of block, module, and full SoC regression test runs is many orders of magnitude faster than simulation
  • Comprehensive, simulation-like debug environment for ease-of-use
  • Hardware platform for software development and debug enables pre-silicon testing
  • Full system integration using real-world stimulus and software for testbenches before first silicon is available
  • VirtuaLAB solutions to create a virtual lab environment of software-only applications and standards-based protocols for the verification of SoCs, without the need for external hardware connections to Veloce
  • Accelerated regression tests speed up post-silicon validation before committing changes to silicon
  • High-speed platform, highly tuned for hardware-software concurrent engineering
  • Connects to multiple software development environments for greater flexibility in verification and debug
  • Fast, integrated compile and place-and-route software delivers consistent results and high-quality route to begin runtime testing
  • Eliminates most silicon respins by running billions of cycles to find hard-to-find bugs missed by traditional methods
  • Capable of handling many interfaces, driving stimulus simultaneously from live and virtual devices
  • Architected to accelerate advanced verification environments based upon UVM, OVM, VMM, and TLM
  • Best vehicle for low power verification using real-world scenarios
  • Simulation-like use model for assertion and coverage based verification
  • Standard queuing support for optimal utilization of emulation resources among various teams and sites

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