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Palladium Z1 Enterprise Emulation System

All Silicon IP All Verification IP

Overview

Verification has become the biggest challenge in SoC development. However, traditional verification tools have not kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle.

As the industry s first datacenter-class emulation system, the Palladium Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.

Compared to the previous generation, the platform, which brings together simulation acceleration and emulation technologies, delivers up to 5X better emulation throughput and, on average, 2.5X better workload efficiency than the closest competitor.

Easy to manage and scale, the platform:
  • Compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation
  • Allocates as many workloads as possible
  • Runs workloads based on priorities
  • Debugs for both pre- and post-silicon bugs

Smart Emulation Resource Utilization

The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform s unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with 4 million gate granularity and scales to 9.2 billion gates.

Compared to the Palladium XP II environment, the new platform offers an up to 44% reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more. The power advantages are a result of:

  • An average of 2.5X better system utilization and number of parallel users
  • Up to 5X better emulation throughput
  • Up to 140MG per hour compile times
  • Superior debug depth and upload speeds

Its rack-based blade architecture results in a 92% smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering 4X better user granularity than its nearest competitor.

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