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Faraday - SoC Design Services

Overview

The increasing complexity, interface, and functionality of SoCs have brought out much more challenges than the traditional chip implementation. To make the highly-integrated system, SoC designer are requested to be equipped with expertise in wise of IP itself, IP integration, IP verification, and HW/SW co-design of system level instead of chip level only. Furthermore, the narrow market window especially can not allow the schedule delay and the miss-out of timing.
With 20 years of IP development, ASIC, and SoC service dedication, Faraday knows deeply about customers most-worried issues and can assist SoC designers to overcome these challenges. To ensure customers successful end-to-end execution, to lower their risk, lessen the effort, and shorten the time-to-market, Faraday has developed the platform based SoC solutions, including SoC design tools, and ready-to-go platforms, which have facilitated many SoC success cases till now, including the SoC projects of networking application with hundreds of million gate-count complexity.

Faraday SoC design service specially comprises the professional consultation by experienced engineers through all design stages, from SoC design engagement, architecture, IP integration, to physical implementation. Involved at the initial specification stage all the way to tape-out, customers can fully rely on Faraday’s SoC consultants to provide recommendations on SoC architectural trade-offs, selecting and configuring the right IPs, and to offer guidance during synthesis and timing closure stages to greatly help reduce implementation time.


Different from traditional ASIC vendors, Faraday provides the services of Architecture Exploration, Integration Express and Verification Express to shorten the implementation hours at each stage.

Architecture Exploration


Architecture exploration and performance verification are essential at the early development stage for designing complex SoCs. Under Faraday’s SoC design service, performance exploration platform and virtual platform are both available to fulfill entire architecture design requirements. In addition, adoption of network-on-chip (NoC) technology contributes to another leap forward in capabilities and flexibilities in tackling complex and large-scale SoC design.

Integration Express


The automatic SoC integration service by in-house design tools. It dramatically reduces the time of front-end design by around two weeks including the whole chip RTL integration and FPGA reference code generation.

Verification Express


To guarantee the quality of integration delivery and to increase the confidence level of tape-out, various techniques are involved to achieve full verification closure. As complexity of chip design grows, coverage metrics are more critical to measure and guide design verification. Integrated tools and rigid verification methodologies are adopted to boost the process toward full coverage.

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