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www.design-reuse-embedded.com |
easics - ASIC / SoC Design & Supply Services |
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Overview easics offers design services for both digital and mixed-signal chips: system-on-chip, ASIC, ASSP and structured ASIC.
Being an independent design services company, easics can provide you with unbiased technology and system architecture advice that perfectly matches your project requirements, budget and schedule. easics, with +30 years experience, is a market leader in the embedded systems digital design by providing unique competence and development platforms that lead to first-time right, reliable and optimized logic and software that is maintainable by the customer. The main target market is to support leading OEMs and semiconductor companies with custom designs and customizable IP blocks for these smart embedded processing systems that can be realized in ASICs / ASSPs / SoCs and in FPGAs. easics HQ is located in Leuven, Belgium For more information, please visit www.easics.com Benefits easics works with leading semiconductor wafer manufacturers such as TSMC, GLOBALFOUNDRIES, UMC, SMIC, ST, NXP, TowerJazz, LFoundry, ON Semi, X-FAB, ams and NEC, and can thus leverage this experience for your project.
We support a wide range of technology nodes: 0.35um, 0.25um, 0.18um, 0.13um, 90nm, 65/55nm, 40nm, 28nm, 16nm. easics has developed a robust and reuse-friendly design methodology to build First Time Right silicon. It uses a coding style that leverages the benefits of a synthesis-based implementation flow to code at the highest possible abstraction level, thus protecting your investment in a readable and maintainable code database. This methodology is proven by a myriad of successful First Time Right projects for customers such as NXP Semiconductors, Cochlear, Keysight, CMOSIS, Sony Depthsensing Solutions, ESA and many others. |
Features
Depending on your requirements easics system architects and design engineers can help you with the following project tasks:
- Feasibility study. - Functional requirements assessment. - System architecture definition. - Hardware-software trade-offs. - Third-party IP selection and integration. - Module level hardware design and verification. - Processor integration and embedded software design. - Top level simulation at RTL and gate level. - Hardware-software co-verification. - Synthesis from RTL level to gate level. - Formal verification. - FPGA prototyping of top-level or sub-level. - Design for test: boundary scan, internal scan. - Physical design and verification. - Static timing analysis (STA). - Power consumption analysis. - Sign-off with technology partner: foundry, packaging, test. - Measurements of prototype ICs in the lab. IP Portfolio Silicon IPSoC Solutions |
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