The EFLX-2.5K Logic IP core is an embeddable FPGA IP core each containing 2,520 Look-Up- Tables (LUTs) in Reconfigurable Building Blocks (RBBs) and 20Kb RAM, patented interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. It is SILICON PROVEN.

The EFLX-2.5K DSP core replaces some RBBs with 40 DSP MACs (22x22 multiplier with 48 bit accumulator). It is compatible with the Logic core so it can be mixed with it in arrays.

The cores can be used standalone or arrayed in square, rectangular or L shapes up to 7x7.

Our patented area-efficient hierarchical interconnect network needs fewer metal layers than conventional FPGAs, enabling the integration of EFLX cores in high volume chips.