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The Arm (R) Cortex(R)-M0 processor is the smallest Arm processor available. The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices.

Fast and easy access to Cortex-M0:
Through the Arm DesignStart online access portal, users have free-of-charge access to Arm IP for system design and simulation as well as a low-cost prototyping package on FPGA to quickly develop proof of concept systems.

The smallest Arm processor:
The code density and energy efficiency benefits of Cortex-M0 mean that it is a natural and cost effective successor to 8/16-bit devices in a wide variety of applications, while retaining tool and binary upwards compatibility with the feature-rich Cortex-M3 and Cortex-M4 processors. For applications requiring even lower consumption or a wider choice of design options, the fully compatible Cortex-M0+ processor is an ideal alternative.

Low power:
The Cortex-M0 processor, which consumes as little as 16uW/MHz (90LP process, minimal configuration) in an area of under 12 K gates, builds on the unrivalled expertise of Arm as a leader in low-power technology and a key enabler for the creation of ultra low-power devices.

With just 56 instructions, it is possible to master quickly the entire Cortex-M0 instruction and its C friendly architecture, making development simple and fast. The option for fully deterministic instruction and interrupt timing makes it easy to calculate response times.

Optimized connectivity:
Designed to support low power connectivity such as Bluetooth Low Energy (BLE), IEEE 802.15 and Z-wave, particularly in analog devices that are increasing their digital functionality to pre-process and communicate data efficiently.

Block Diagram


RISC Processor Core
  • High performance 32-bit CPU
  • Deterministic operation
  • Compact, low latency pipeline
Thumb(R)-2 Technology
  • Optimal blend of 16/32-bit instructions
  • 30% smaller code size than 8-bit devices
  • No compromise on performance
Tools and RTOS support
  • Broad 3rd party tools support
  • Cortex Microcontroller Software Interface Standard (CMSIS)
  • Maximizes software reuse
CoreSight Debug and Trace
  • JTAG or 2-pin Serial Wire Debug (SWD) connection
  • Support for multiple processors
Low Power Modes
  • Integrated sleep state support
  • Multiple power domains
  • Architected software control
Nested Vectored Interrupt Controller (NVIC)
  • Low latency, low jitter interrupt response
  • No need for assembly programming
  • Interrupt service routines in pure C
Cortex Microcontroller Software Interface Standard (CMSIS)
  • Vendor independent hardware abstraction layer
  • Enables consistent and simple software interfaces to the processor
  • Reduced learning curve for microcontroller developers
Maturity:Shipping in many parts Target Process Node: any

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