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Overview

SiFive’s E31 RISC-V Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in an ultra-power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, wearables, and embedded microcontrollers.

Applications

smart IoT, wearables,embedded microcontrollers.

Block Diagram

Features

  • Fully compliant with the RISC-V ISA specification
  • RV32IMAC Support:
    • RV32I - 32-bit RISC-V with 32 integer registers
    • Integer Multiplication and Division (M) support
    • Atomic Mode (A) support for high-performance, portable software
    • Compressed Mode (C) support for better code density
  • Machine and User Mode Support
  • In-order, 5-6 stage variable pipeline
  • Advanced Memory Subsystem:
    • 16KB, 2-way Instruction Cache
    • Instruction Tightly Integrated Memory (ITIM) option
    • Up to 64KB Data Tightly Integrated Memory (DTIM) support
  • Efficient and Flexible Interrupts:
    • Local interrupts w/ vectored addresses - up to 16
    • Platform Level Interrupt Controller (PLIC) - 255 interrupts w/ 7 priority levels
    • RISC-V Core Local Interruptor (CLINT) - 1 timer, 1 SW
  • 8-Region Physical Memory Protection (PMP)
  • High performance TileLink Interface
  • 1.61 DMIPS/MHz
  • 2.73 Coremark/MHz

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