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Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. The APS3V processor offers the RISC-V ISA RV32IMC features, with the full integer instruction set, compressed instructions and multiply and divide. In addition it implements the privilege features with Machine and User modes. The Cortus APS3V processor is designed to be both power and silicon efficient. The standard implementation requires 17 000 gates. The four stage pipeline offers a good compromise between throughput and maximum operating frequency, for example in 40 nm an Fmax of at least 1 GHz max can be achieved. The Cortus APS3V processor features a Harvard architecture with AXI4 Lite bus interfaces. This ensures wide compatibility with other peripheral IP, allowing the standard peripherals from Cortus to be complemented by other IP. Full debug support is implemented through Cortus standard debug interface and tools (GDB and OpenOCD).


RISC-V 32 bit ISA (RV32)
Integer Instruction Set (I)
Compressed Instruction Set (C)
Integer Multiply & Divide (M)
Machine and User Modes
4 Stage Pipeline
AXI4 Lite Bus (Instruction and Data)
Small Silicon Footprint
Full Peripheral Set
Hardware Breakpoints
Full Toolchain and IDE with no Licence Fee

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