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ZSP981 offers an optimal balance of performance, power and area to handle complex signal processing algorithms for new and evolving wireless technologies such as LTE-Advanced, 802.11ac and more. With the enhanced vector processing capabilities the highly flexible architecture enables efficient implementations of a broad range of algorithms such as image processing also.


  • Based on scalable ZSP superscalar architecture - reuse software as application evolves
  • Compiler friendly architecture - orthogonal instruction set
  • Very good code density
  • Optimal balance of performance, power and area to meet the most stringent application requirements
  • Easy to use, easy to program
  • Broad portfolio of optimized field proven application software, cutting edge development tools, complete ecosystem and exceptional services to help users from concept to market


  • 6 issue superscalar DSP core
  • Scalar and 4 Vector Units
  • Upto 82 billion MACs per second at 1.2 GHz
  • Compatible with previous generation ZSP cores
  • Instruction set optimized for vector processing applications
  • Vectorizing compiler
  • Custom Instruction support using high performance, high bandwidth Z.Turbo coprocessor ports
  • 8GB addressable space
  • Tightly coupled Instruction and Data memory
  • High performance Instruction and Data caches
  • AXI interface
  • Multiple low power modes of operation
  • Integrated low latency interrupt controller, timers, DMA and other peripherals

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