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Overview

IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and running a mix of trusted firmware and user application code.

Benefits

IQonIC Works RV32IC_P5 Core can be used in both ASIC- and FPGA-based design flows, and offers the following features:

  • RISC-V RV32I base instruction set, compliant with RISC-V User-Level ISA V 2.2.
  • RISC-V "A" standard extension instructions for critical sections in a uniprocessor system.
  • RVC standard 16-bit compressed instructions for common RV32 instructions, for reduced code size.
  • Machine-mode and user-mode privileged architecture with direct physical addressing of memory, compliant with RISC-V Privileged Architecture Version 1.10.
  • Optional standard physical memory protection (PMP) with configurable number of entries, to support protected execution of application code.
  • Optional "N" standard extension for user-mode exception and interrupt handling.
  • Optional "M" standard extension for integer multiplication and division instructions.
  • Provision for application-specific instruction set extensions, e.g. for DSP operations.
  • 20 extended interrupts, plus timer and software interrupts.
  • Provision for external interrupt controller for additional interrupt sources.
  • All interrupts and exceptions, including those delegated to user mode, may be vectored for fast interrupt response.
  • Wait-for-interrupt instruction supports clock gating for low-power idle state.
  • 5-stage pipeline comprising fetch, decode, execute, memory access, and write back stages.
  • Optional branch prediction, branch target buffer, and return address stack, with configurable sizes and associativity, for reduced branch latency.
  • Tightly-coupled scratchpad memory interfaces for ASIC ROM and SRAM memories or FPGA block memories.
  • Optional instruction and write-back data cache memories with configurable line sizes, number of sets, and associativity.
  • AHB-Lite interfaces for extended memory and memory-mapped I/O.
  • GNU tool chain and Eclipse development environment for firmware development.
  • Firmware and virtual prototype development supported by ASTC's VLAB system-level design tools.
  • Accompanying machine-mode timers (AHB and APB versions) operating in processor clock domain or separate always-on timer clock domain.
  • Accompanying platform-level interrupt controller (PLIC) for up to 1023 interrupt sources and separate machine-mode and user-mode targets.

Block Diagram

Features

IQonIC Works RISC-V Cores come with a full suite of design IP including:

  • RISC-V IP (Core and Platform IP) package
  • Synthesizable RTL
  • Verification IP, Simulation test bench and basic test cases
  • Example synthesis scripts
  • Documentation
    • Data sheet, integration guide, programmer's guide
  • Reference designs
    • FPGA project files and sample firmware source code

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