The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including (IMAFD) standard instructions, 16-bit compression instructions, and for user-level interrupts. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. Its extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, N45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support.