IQonIC Works RISC-V Timer IP comprises a suite of timers, each conforming to the RISC-V standard machine timer specification. For simple applications in which the timer counts processor-clock cycles, variants are provided without clock-domain crossing (CDC). Alternatively, for low-power applications in which the system clock may be gated-off or disabled, IQONIC Works also offers a variant with CDC counts of cycles of a low-frequency always-on clock (e.g., a clock provided by a low-power 32kHz oscillator). Variants of the timer with AHB bus interfaces allow for use in systems with complex bus structures. Alternatively, variants with APB bus interfaces allow for use in small systems with simple APB-only bus structures.