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BCH based Error Correcting Code FEC

Overview

Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC


The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.


Symbol Size is 1 bit and variables are 'm' bits wide for Galois Field operations.


Every symbol and primitive polynomial used of degree 'm' and 'n' is ((1<<'m')-1) .Shortened 'n_short' is less than 'n' where symbols ('n' – 'n_short') are 0 . If the code has 't' error correcting capability then 'k' = 'n' – 2*'t' = no. of message symbols.


RTL is completely configurable for 'm' , 'n_short' or 't'. Typically, but not necessarily 'm' lies between 5 to 15 ECC, number of parity symbols is 2*'t'.


Errors_correctable are upto 'tt', if more than 'tt' errors then indicated as uncorrectable.


The Error correcting Code consists of:


Encoder:

  • It has programmable input data bus width. The whole encoding can be completed in 0 cycle


Decoder:

  • Syndrome Calculator: It can generate all syndromes in 0 clocks, or serially in as large as 'n_short' clocks

  • BerlekampMasy Circuit: it generates error locator polynomial for Chien search engine

  • Parallel Chien Search Engine: It finds error locations in as little as 0 clock or as large as 'n_short' clocks

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