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CEVA-XC12 Multi-gigabit SDR Processor

Overview

The CEVA-XC12 is the first DSP architecture that offers the raw performance and power efficiency required for multi-gigabit class modems. This flexible architecture with multiple options enables it to be customized, configured, and scaled to address applications such as smartphones and other terminals, advanced and centralized access points, small cells, macro cells and cloud RAN (C-RAN).


CEVA-XC12 supports:



  • 5G use cases

  • LTE-Advanced Pro Evolution

  • enhanced Mobile Broadband (eMBB)

  • Licensed Assisted Access (LAA)

  • MulteFire carrier aggregation

  • LTE/Wi-Fi Aggregation(LWA)

  • cellular V2X

  • Wi-Fi 802.11ax

  • WiGig 802.11ad

  • Fixed Wireless Access (FWA)

  • Virtual Reality (VR) systems

  • CEVA-XC12 is underpinned by a host of technology advances, including a new micro-architecture to meet high frequency requirements and ultra-low power consumption. The CEVA-XC12 can operate at 1.8 GHz in 10 nm while using 50% less power than its predecessor, the CEVA-XC4500. Massive computation capabilities enable it to maintain a high bit rate via the use of quad-vector processor engines, which approach 1 Tera-operations per second (TOPs) performance.

  • Unique high-precision arithmetic achieves optimal resolution with up to 256x256 dimension matrix processing. Specialized instructions boost all baseband processing components, and new core streaming interfaces facilitate ultra-low latency transfers between cores or accelerators. A control plane for massive-user management and for multi-RAT (Radio Access Technology) systems incorporates a Scalar Processing Unit (SPU) with a CoreMark/MHz score of 4.4, and is designed to handle the huge number of users required for LTE MTC and 5G IoT.

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