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FlexLLI MIPI Low Latency Interface (MIPI LLI) Digital Controller Interchip Connectivity IP

All Silicon IP

Overview

Arteris FlexLLI digital controller IP is the industry s first and only silicon-proven implementation of the MIPI Low Level Interface (LLI) specification. Arteris FlexLLI digital controller IP can connect two chips together to create a single virtual chip , with both chips sharing a single DRAM. LLI s initial expected purpose is to connect a mobile phone applications processor to a mobile phone modem. The ~80ns round-trip latency of an LLI connection is fast enough for the modem to share the application processors RAM. This enables the phone manufacturer to remove the modems dedicated RAM chip from the phones bill of materials (BOM). FlexLLI can also be used in non-mobile applications where low latency and high bandwidth between chips is required, such as co-processing and companion chip applications. FlexLLI does not require a runtime software stack, unlike other standards like USB and PCIe.

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