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56G Ethernet PHY in TSMC (16nm, 7nm)

Overview

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measurement techniques, the 56G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The PHY is small in area, low in power consumption, and high in performance, supporting channel loss of 35dB and meeting the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects

The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the DesignWare Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.

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